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ADNS-5050

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
13
LED Mode
For optimized tracking performance, the LED is in DC
mode when motion is detected, and ADNS-5050 will
pulse the LED when the mouse is in idle state. To force the
LED into always DC mode, kindly refer to register 0x22.
Synchronous Serial Port
The synchronous serial port is used to set and read pa-
rameters in the ADNS-5050, and to read out the motion
information.
The port is a three wire serial port. The host micro-con-
troller always initiates communication; the ADNS-5050
never initiates data transfers. SCLK, SDIO, and NCS may
be driven directly by a micro-controller. The port pins may
be shared with other SPI slave devices. When the NCS pin
is high, the inputs are ignored and the output is tri-stated.
The lines that comprise the SPI port:
SCLK: Clock input. It is always generated by the master
(the micro-controller).
SDIO: Input and Output data.
NCS: Chip select input (active low). NCS needs to be
low to activate the serial port; otherwise, SDIO
will be high Z, and SDIO & SCLK will be ignored.
NCS can also be used to reset the serial port in
case of an error.
Write Operation
1
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 21
D
0
D
5
D
6
D
7
A
0
A
1
A
2
A
3
A
4
A
5
A
6
1A
6
D
4
D
3
D
2
D
1
SCLK
NCS
SDIO
SDIO DRIVEN BY MICRO-CONTROLLER
SDIO Setup and Hold Time
t
setup
1/(2f )
SCLK
t
hold
SCLK
SDIO
1/(2f )
SCLK
Chip Select Operation
The serial port is activated after NCS goes low. If NCS
is raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true for
all transactions. After a transaction is aborted, the nor-
mal address-to-data or transaction-to-transaction delay
is still required before beginning the next transaction. To
improve communication reliability, all serial transactions
should be framed by NCS. In other words, the port should
not remain enabled during periods of non-use because
ESD and EFT/B events could be interpreted as serial com-
munication and put the chip into an unknown state. In ad-
dition, NCS must be raised after each burst-mode transac-
tion is complete to terminate burst-mode. The port is not
available for further use until burst-mode is terminated.
Write Operation
Write operation, de ned as data going from the micro-
controller to the ADNS-5050, is always initiated by the
micro-controller and consists of two bytes. The  rst byte
contains the address (seven bits) and has a “1” as its MSB
to indicate data direction. The second byte contains the
data. The ADNS-5050 reads SDIO on rising edges of SCLK.
14
Read Operation
A read operation, de ned as data going from the ADNS-5050 to the micro-controller, is always initiated by the micro-
controller and consists of two bytes. The  rst byte contains the address, is sent by the micro-controller over SDIO, and
has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-5050 over
SDIO. The sensor outputs SDIO bits on falling edges of SCLK and samples SDIO bits on every rising edge of SCLK.
Read Operation
Microcontroller to ADNS-5050 Hando
ADNS-5050 to Microcontroller Hando
NOTE:
The 0.5/f
SCLK
minimum high state of SCLK is also the minimum SDIO data hold time of the ADNS-5050. Since the falling edge of SCLK is actually the
start of the next read or write command, the ADNS-5050 will hold the state of data on SDIO until the falling edge of SCLK.
D
0
t
DLY
t
HOLD
R/W BIT OF NEXT ADDRESS
SCLK
SDIO
DETAIL "B"
ADNS-5050 TO
MICROCONTROLLER
SDIO HANDOFF
DRIVEN BY MICRORELEASED BY 5050
D
7
D
6
A
0
A
1
DETAIL "A"
MICROCONTROLLER
TO ADNS-5050
SDIO HANDOFF
SDIO
SCLK
t
SETUP
t
SRAD
0 ns, MIN.
t
DLY
0 ns, MIN.
t
DLY
Hi-Z
1
0
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
D
0
D
5
D
6
D
7
A
0
A
1
A
2
A
3
A
4
A
5
A
6
D
4
D
3
D
2
D
1
SCLK
CYCLE #
SCLK
SDIO
SDIO DRIVEN BY MICRO-CONTROLLER SDIO DRIVEN BY ADNS-5050
DETAIL "A" DETAIL "B"
15
Required Timing between Read and Write Commands
There are minimum timing requirements between read
and write commands on the serial port.
If the rising edge of the SCLK for the last data bit of the
second write command occurs before the required delay
(t
sww
), then the  rst write command may not complete
correctly.
Timing between Two Write Commands
If the rising edge of SCLK for the last address bit of the
read command occurs before the required delay (t
SWR
),
the write command may not complete correctly.
Timing between Write and Read Commands
During a read operation SCLK should be delayed at least
t
SRAD
after the last address data bit to ensure that the
ADNS-5050 has time to prepare the requested data. The
falling edge of SCLK for the  rst address bit of either the
read or write command must be at least t
SRR
or t
SRW
after
the last SCLK rising edge of the last data bit of the previous
read operation.
Timing between Read and Either Write or Subsequent Read Commands
SCLK
t
SWW
WRITE OPERATION
ADDRESS DATA
WRITE OPERATION
ADDRESS DATA
SCLK
t
SRAD
READ OPERATION
ADDRESS
NEXT READ
or WRITE OPERATION
ADDRESS
• • •
• • •
t
SRW
&
t
SRR
DATA
SCLK
t
SWR
WRITE OPERATION
ADDRESS DATA
NEXT READ OPERATION
ADDRESS
• • •
• • •
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ADNS-5050

Mfr. #:
Buy ADNS-5050
Manufacturer:
Broadcom / Avago
Description:
IC USB OPT MOUSE SENSOR HS 8-DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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