16
Notes on Power-up and Reset
The ADNS-5050 does not perform an internal power up
self-reset. There are two ways to reset the chip, either as-
sert low NRESET pin or by writing 0x5a to register 0x3a. A
full reset will thus be executed. Any register settings must
then be reloaded.
Burst Mode Operation
Burst mode is a special serial port operation mode that
may be used to reduce the serial transaction time for a
motion read. The speed improvement is achieved by con-
tinuous data clocking to or from multiple registers with-
out the need to specify the register address, and by not
requiring the normal delay period between data bytes.
Burst mode is activated by reading the Motion_Burst reg-
ister. The ADNS-5050 will respond with the contents of the
Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shutter_Lower,
Maximum_Pixel and Pixel_Sum registers in that order. The
burst transaction can be terminated anywhere in the se-
quence after the Delta_X value by bringing the NCS pin
high. After sending the register address, the micro-con-
troller must wait tSRAD and then begin reading data. All
data bits can be read with no delay between bytes by driv-
ing SCLK at the normal rate. The data are latched into the
output bu er after the last address bit is received. After
the burst transmission is complete, the micro-controller
must raise the NCS line for at least tBEXIT to terminate
burst mode. The serial port is not available for use until
it is reset with NCS, even for a second burst transmission.
Avago Technologies highly recommends the usage of burst
mode operation in optical mouse sensor design applications.
Motion Burst Timing
Notes on Power Down
The ADNS-5050 can be set in Power Down mode by set-
ting bit 1 of register 0x0d. In addition, the SPI port should
not be accessed during power down. (Other ICs on the
same SPI bus can be accessed, as long as the sensor’s NCS
pin is not asserted.) The table below shows the state of
various pins during power down. There are 2 ways to exit
power down, either assert low NRESET pin or by writing
0x5a to Register 0x3a. A full reset will thus be executed.
Wait for t
WAKEUP
before accessing the SPI port. Any regis-
ter settings must then be reloaded.
Pin Power Down Active
NRESET Functional
NCS Functional*
SDIO Functional*
SCLK Functional*
XY_LED Power Down
* NCS pin must be held to 1(high) if SPI bus is shared with other
devices. It can be in either state if the sensor is the only device in
addition to the controller microprocessor.
NOTE: There is long wakeup time from power down.
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins during
power-up and reset.
State of Signal Pins After V
DD
is Valid
Pin During Reset After Reset
NCS Ignored Functional
SDIO Ignored Depends on NCS
SCLK Ignored Depends on NCS
XY_LED Hi-Z Functional
MOTION_BURST REGISTER ADDRESS READ FIRST BYTE
FIRST READ OPERATION READ SECOND BYTE READ THIRD BYTE
SCLK
• • •
• • •
t
SRAD
