Data Sheet AD7923
Rev. D | Page 17 of 24
If 2.5 V is applied to the REF
IN
pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the range bit in the control register.
MODES OF OPERATION
The AD7923 has a number of different modes of operation,
which are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application
requirements. The mode of operation of the AD7923 is
controlled by the power management bits, PM1 and PM0, in
the control register, as detailed in Table 8. When power supplies
are first applied to the AD7923, care should be taken to ensure
that the part is placed in the required mode of operation (see
the Powering Up the AD7923 section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance where the user does not have to worry about power-up
time since the AD7923 remains fully powered at all times.
Figure 20 shows the general diagram of the operation of the
AD7923 in this mode.
The conversion is initiated on the falling edge of
CS
and the
track-and-hold enters hold mode, as described in the Serial
Interface section. The data presented to the AD7923 on the
DIN line during the first 12 clock cycles of the data transfer is
loaded into the control register (provided the write bit is set to
1). The part remains fully powered up in normal mode at the
end of the conversion as long as PM1 and PM0 are set to 1 in
the write transfer during that same conversion. To ensure
continued operation in normal mode, PM1 and PM0 must both
be loaded with 1 on every data transfer, assuming a write
operation is taking place. If the write bit is set to 0, the power
management bits are left unchanged and the part remains in
normal mode.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. The track-and-hold go
back into track on the 14th SCLK falling edge.
CS
may then idle
high until the next conversion or may idle low until sometime
prior to the next conversion (effectively idling
CS
low).
For specified performance, the throughput rate should not
exceed 200 kSPS, which means there should be no less than 5 µs
between consecutive falling edges of
CS
when converting. The
actual frequency of the SCLK used determines the duration of
the conversion within this 5 µs cycle; however, once a conver-
sion is complete, and
CS
has returned high, a minimum of the
quiet time, t
QUIET
, must elapse before bringing
CS
low again to
initiate another conversion.
1
12
CS
SCLK
DOUT
DIN
16
2 LEADING ZEROS + 2 CHANNEL IDENTIFIER BITS
+ CONVERSION RESULT
DATA INTO CONTROL REGISTER
CONTROL REGISTER DATA IS LOADED
ON THE FIRST 12 SCLK CYCLES.
03086-020
Figure 20. Normal Mode Operation
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7923 is powered
down. The part retains information in the control register
during full shutdown. The AD7923 remains in full shutdown
until the power management bits in the control register, PM1
and PM0, are changed.
If a write to the control register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, normal mode, the part begins to power up on the
CS
rising edge. The track-and-hold that was in hold while the part
was in full shutdown returns to tracking on the 14th SCLK
falling edge. A full 16-SCLK transfer must occur to ensure that
the control register contents are updated; however, the DOUT
line is not driven during this wake-up transfer.
To ensure that the part is fully powered up, t
POWER UP
(t
12
) should
have elapsed before the next
CS
falling edge; otherwise invalid
data is read if a conversion is initiated before this time.
Figure 21 shows the general diagram for this sequence.
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7923 automatically enters shutdown at the
end of each conversion when the control register is updated. When
the part is in shutdown, the track-and-hold is in hold mode.
Figure 22 shows the general diagram of the operation of the
AD7923 in this mode. In shutdown mode all internal circuitry
on the AD7923 is powered down. The part retains information
in the control register during shutdown. The AD7923 remains
in shutdown until the next
CS
falling edge it receives. On this
CS
falling edge, the track-and-hold that was in hold while the
part was in shutdown returns to tracking. Wa ke -up time from
auto shutdown is 1 µs maximum, and the user should ensure
that 1 µs has elapsed before attempting a valid conversion. When
running the AD7923 with a 20 MHz clock, one dummy 16 SCLK
transfer should be sufficient to ensure that the part is fully powered
up. During this dummy transfer, the contents of the control register
should remain unchanged, therefore the write bit should be 0
on the DIN line. Depending on the SCLK frequency used, this
dummy transfer may affect the achievable throughput rate of the
part, with every other data transfer being a valid conversion
result. If, for example, the maximum SCLK frequency of 20 MHz is
used, the auto shut-down mode could be used at the full through-
out rate of 200 kSPS without affecting the throughput rate at all.
