AD7923 Data Sheet
Rev. D | Page 22 of 24
The connection diagram is shown in Figure 30. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
CS
and, as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC, and under certain conditions equidistant sampling
might not be achieved.
V
DRIVE
AD7923
1
ADSP-218x
1
SCLK
DR
RFS
TFS
DT
SCLK
DOUT
CS
DIN
1
ADDITIONAL PINS REMOVED FOR CLARITY.
V
DD
03086-030
Figure 30. Interfacing to the ADSP-218x
The timer register, for instance, is loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (that is, AX0 = TX0), the state of the SCLK is
checked. The DSP waits until the SCLK has gone high, low, and
high before the transmission starts. If the timer and SCLK
values are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, the data can be transmitted,
or it can wait until the next clock edge.
For example, if the ADSP-2189 has a 20 MHz crystal such that it
has a master clock frequency of 40 MHz, then the master cycle
time is 25 ns. If the SCLKDIV register is loaded with the value
3, then a SCLK of 5 MHz is obtained, and eight master clock
periods elapse for every SCLK period. Depending on the
throughput rate selected, if the timer registers are loaded with
the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation
results in nonequidistant sampling since the transmit
instruction occurs on a SCLK edge. If the number of SCLKs
between interrupts is an integer of N, equidistant sampling is
implemented by the DSP.
AD7923-to-DSP563xx
The connection diagram in Figure 31 shows how the AD7923
can be connected to the synchronous serial interface (ESSI) of
the DSP563xx family of DSPs from Motorola. Each ESSI (two
on board) is operated in synchronous mode (SYN bit in CRB =
1), with an internally generated word length frame sync for
both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal
operation of the ESSI is selected by making MOD = 0 in the
CRB. Set the word length to 16 by setting bits WL1 = 1 and
WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so
the frame sync is negative. It should be noted that for signal
processing applications, it is imperative that the frame synchro-
nization signal from the DSP563xx provides equidistant
sampling.
In the example shown in Figure 31, the serial clock is taken
from the ESSI, therefore the SCK0 pin must be set as an output,
SCKD = 1. The V
DRIVE
pin of the AD7923 takes the same supply
voltage as the DSP563xx, which allows the ADC to operate at a
higher voltage than the serial interface, that is, DSP563xx, if
necessary.
AD7923
1
DSP563xx
1
SCK
SRD
STD
SC2
SCLK
DOUT
CS
DIN
V
DRIVE
1
ADDITIONAL PINS REMOVED FOR CLARITY.
V
DD
03086-031
Figure 31. Interfacing to the DSP563xx
