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AD7923BRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD7923
Rev. D | Page 3 of 24
SPECIFICATIONS
AV
DD
= V
DRIVE
= 2.7 V to 5.25 V, REF
IN
= 2.5 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 50 kHz sine wave, f
SCLK
= 20 MHz
Signal-to-(Noise + Distortion) (SINAD)
2
70 dB min @ 5 V, –40°C to +85°C
69 dB min @ 5 V, 85°C to 125°C, typ 70 dB
69 dB min @ 3 V typ 70 dB, –40°C to +125°C
Signal-to-Noise (SNR)
2
70 dB min
Total Harmonic Distortion (THD)
2
−77 dB max @ 5 V typ, −84 dB
−73
dB max
@ 3 V typ,−77 dB
Peak Harmonic or Spurious Noise −78 dB max @ 5 V typ, −86 dB
(SFDR)
2
−76 dB max @ 3 V typ, −80 dB
Intermodulation Distortion (IMD)
2
f
A
= 40.1 kHz, f
B
= 41.5 kHz
Second Order Terms −90 dB typ
Third Order Terms −90 dB typ
Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation −85 dB typ f
IN
= 400 kHz
Full Power Bandwidth 8.2 MHz typ @ 3 dB
1.6 MHz typ @ 0.1 dB
DC ACCURACY
2
Resolution 12 Bits
Integral Nonlinearity ±1 LSB max
Differential Nonlinearity
−0.9/+1.5
LSB max
Guaranteed no missed codes to 12 bits
0 V to REF
IN
Input Range Straight binary output coding
Offset Error ±8 LSB max Typ ±0.5 LSB
Offset Error Match ±0.5 LSB max
Gain Error ±1.5 LSB max
Gain Error Match ±0.5 LSB max
0 V to 2 × REF
IN
Input Range −REF
IN
to +REF
IN
biased about REF
IN
with twos
complement output coding
Positive Gain Error ±1.5 LSB max
Positive Gain Error Match ±0.5 LSB max
Zero-Code Error ±8 LSB max Typ ±0.8 LSB
Zero-Code Error Match
±0.5
LSB max
Negative Gain Error ±1 LSB max
Negative Gain Error Match ±0.5 LSB max
ANALOG INPUT
Input Voltage Range 0 to REF
IN
V Range bit set to 1
0 to 2 × REF
IN
V Range bit set to 0, AV
DD
= 4.75 V to 5.25 V
DC Leakage Current ±1 µA max
Input Capacitance 20 pF typ
REFERENCE INPUT
REF
IN
Input Voltage 2.5 V ±1% specified performance
DC Leakage Current ±1 µA max
REF
IN
Input Impedance 36 kΩ typ f
SAMPLE
= 200 kSPS
LOGIC INPUTS
Input High Voltage, V
INH
0.7 × V
DRIVE
V min
Input Low Voltage, V
INL
0.3 × V
DRIVE
V max
Input Current, I
IN
±1 µA max Typ 10 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
3
10 pF max
AD7923 Data Sheet
Rev. D | Page 4 of 24
Parameter B Version
1
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
– 0.2 V min I
SOURCE
= 200 µA, AV
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4 V max I
SINK
= 200 µA
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance
3
10
pF max
Output Coding Twos Complement Coding bit set to 0
Straight (Natural)
Binary
Coding bit set to 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz
300 ns max Sinewave input
300 ns max Full-scale step Input
Throughput Rate 200 kSPS max See Serial Interface section
POWER REQUIREMENTS
AV
DD
2.7/5.25 V min/max
V
DRIVE
2.7/5.25 V min/max
I
DD
4
Digital I/Ps = 0 V or V
DRIVE
During Conversion 2.7 mA max AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
2.0 mA max AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
Normal Mode (Static) 600 µA typ AV
DD
= 2.7 V to 5.25 V, SCLK on or off
Normal Mode (Operational) f
SAMPLE
= 200 kSPS
1.5
mA max
AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
1.2 mA max AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
Using Auto Shutdown Mode f
SAMPLE
= 200 kSPS 900 µA typ AV
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS
650 µA typ AV
DD
= 2.7 V to 3.6 V, f
SAMPLE
= 200 kSPS
Auto Shutdown (Static) 0.5 µA max SCLK on or off (20 nA typ)
Full Shutdown Mode 0.5 µA max SCLK on or off (20 nA typ)
Power Dissipation
4
Normal Mode (Operational) f
SAMPLE
= 200 kSPS 7.5 mW max AV
DD
= 5 V, f
SCLK
= 20 MHz
3.6 mW max AV
DD
= 3 V, f
SCLK
= 20 MHz
Auto Shutdown (Static) 2.5 µW max AV
DD
= 5 V
1.5 µW max AV
DD
= 3 V
Full Shutdown Mode 2.5 µW max AV
DD
= 5 V
1.5 µW max AV
DD
= 3 V
1
Temperature range: B Version: −40°C to +125°C.
2
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
Data Sheet AD7923
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS
AV
DD
= 2.7 V to 5.25 V, V
DRIVE
≤ AV
DD
, REF
IN
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Limit at T
MIN
, T
MAX
Parameter AV
DD
= 3 V AV
DD
= 5 V Unit Description
f
SCLK
2
10 10 kHz min
20 20 MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
t
QUIET
50 50 ns min
Minimum quiet time required between
CS
rising edge and start of next
conversion
t
2
10 10 ns min
CS
to SCLK set-up time
t
3
3
35 30 ns max
Delay from
CS
until DOUT three-state disabled
t
4
3
40 40 ns max Data access time after SCLK falling edge
t
5
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
10 10 ns min SCLK to DOUT valid hold time
t
8
4
15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance
t
9
10
ns min
DIN set-up time prior to SCLK falling edge
t
10
5 5 ns min DIN hold time after SCLK falling edge
t
11
20 20 ns min
Sixteenth SCLK falling edge to
CS
high
t
12
1 1 µs max Power-Up time from full power-down/auto shutdown mode
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of AV
DD
) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
DRIVE
.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t
8
, is the true bus relinquish
time of the part and is independent of the bus loading.
200µ
A I
OL
200µA
I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
03086-002
Figure 2. Load Circuit for Digital Output Timing Specification
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7923BRUZ

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Buy AD7923BRUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 4CH 200 kSPS 12-Bit W/ Sequencer
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