10
AT94S Secure Family
2314D–FPSLI–2/04
Reading Read instructions are initiated similarly to write instructions. However, with the R/W bit in
the Device Address set to one. There are three variants of the read instruction: current
address read, random read and sequential read.
For all reads, it is important to understand that the internal Data Byte address counter
maintains the last address accessed during the previous read or write operation, incre-
mented by one. This address remains valid between operations as long as the chip
power is maintained and the device remains in 2-wire access mode (i.e., SER_EN
is
driven Low). If the last operation was a read at address n, then the current address
would be n + 1. If the final operation was a write at address n, then the current address
would again be n + 1 with one exception. If address n was the last byte address in the
page, the incremented address n + 1 would “roll over” to the first byte address on the
next page.
CURRENT ADDRESS READ: Once the Device Address (with the R/W
select bit set to
High) is clocked in and acknowledged by the Configurator, the Data Byte at the current
address is serially clocked out by the Configurator in response to the clock from the pro-
grammer. The programmer generates a Stop Condition to accept the single byte of data
and terminate the read instruction.
A Current Address Read instruction consists of
a Start Condition
a Device Address with R/W
= 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
RANDOM READ: A Random Read is a Current Address Read preceded by an aborted
write instruction. The write instruction is only initiated for the purpose of loading the
EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address
Bytes are clocked in and acknowledged by the Configurator, the programmer immedi-
ately initiates a Current Address Read.
A Random Address Read instruction consists of :
a Start Condition
a Device Address with R/W
= 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge bit from the Configurator
a Start Condition
a Device Address with R/W
= 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
11
AT94S Secure Family
2314D–FPSLI–2/04
SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a
Random Address Read. After the programmer receives a Data Byte, it may respond
with an Acknowledge Bit. As long as the Configurator receives an Acknowledge Bit, it
will continue to increment the Data Byte address and serially clock out sequential Data
Bytes until the memory address limit is reached.
(1)
The Sequential Read instruction is
terminated when the programmer does not respond with an Acknowledge Bit but
instead generates a Stop Condition following the receipt of a Data Byte.
Note: 1. If an ACK is sent by the programmer after the data in the last memory address is sent
by the configurator, the internal address counter will “rollover” to the first byte address
of the memory array and continue to send data as long as an ACK is sent by the
programmer.
Programmer Functions The following programmer functions are supported while the Configurator is in program-
ming mode (i.e., when SER_EN
is driven Low):
1. Read the Manufacturer’s Code and the Device Code (optional for ISP).
2. Program the device.
3. Verify the device.
In the order given above, they are performed in the following manner.
Reading Manufacturer’s
and Device Codes
On AT17LV010 Configurator, the sequential reading of these bytes are accomplished by
performing a Random Read at EEPROM Address 040000H.
The correct codes are:
Manufacturers Code -Byte 0 1E
Device Code - Byte 1 F7 AT17LV010
Note: The Manufacturer’s Code and Device Code are read using the byte ordering specified for
Data Bytes; i.e., LSB first, MSB last.
Programming the Device All the bytes in a given page must be written. The page access order is not important but
it is suggested that the Configurator be written sequentially from address 0. Writing is
accomplished by using the cSDA and cSCK pins.
Important Note on AT94S Series
Configurators Programming
The first byte of data will not be cached for read back during FPGA Configuration (i.e.,
when SER_EN
is driven High) until the Configurator is power-cycled.
Verifying the Device All bytes in the Configurator should be read and compared to their intended values.
Reading is done using the cSDA and cSCK pins.
In-System Programming
Applications
The AT94S Series Configurators are in-system (re)programmable (ISP). The example
shown on the following page supports the following programmer functions:
1. Read the Manufacturer’s Code and the Device Code.
2. Program the device.
3. Verify the device data.
While Atmel’s Secure FPSLIC Configurators can be programmed from various sources
(e.g., on-board microcontrollers or PLDs), the applications shown here are designed to
facilitate users of our ATDH2225 Configurator Programming Cable. The typical system
setup is shown in Figure 3.
The pages within the configuration EEPROM can be selectively rewritten.
This document is limited to example implementations for Atmel’s AT94S application.
12
AT94S Secure Family
2314D–FPSLI–2/04
Figure 3. Typical System Setup
The diode connection between the AT94S’ RESET
pin and the SER_EN signal allows
the external programmer to force the FPGA into a reset state during ISP. This eliminates
the potential for contention on the cSCK line. The pull-up resistors required on the lines
to RESET
, CON and INIT are present on the inputs (internally) to the AT94S FPSLIC,
see Figure 4.
Figure 4. ISP of the AT17LV512/010 in an AT94S FPSLIC Application
Note: 1. Configurator signal names are shown in parenthesis.
PC
Secure
FPSLIC
Target System
10-pin
Ribbon
Cable
Programming
Dongle
In-System
Programming
Connector
Header
ATDH2225
10
Secure
FPSLIC
2
4
6
8
10
cSDA 1
cSCK 3
5
7
9
SER_EN
V
CC
GND
AT94S
(SER_EN)
DATA0 (cSDA)
(1)
CLK (cSCK)
(1)
INIT (RESET/OE)
(1)
CON (CE)
(1)
RESET
GND
RESET
M2
M0

AT94S40AL-25BQC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Field Programmable Gate Array ASICS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet