7
AT94S Secure Family
2314D–FPSLI–2/04
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB.
EEPROM Address is Defined as:
Note: where X
n
... X
0
is (PAGE_COUNT)\b
T_BYTE
T_PAGE
AT17LV010 0000 000x
9
x
8
x
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
000 0000
AT17LV010 128
AT17LV010 1024
cSDA
cSCK
cSDA
cSCK
DATA BIT
STOP CONDITION
cSDA
cSCK
ACK BIT
cSDA
cSCK
ACK
START CONDITION
Programming Summary:
Write to Whole Device
SER_EN Low
PAGE_COUNT 0
START
Send Start Condition
BYTE_COUNT 0
Send Device Address
($A6)
ACK?
Send MSB of
EEPROM Address
(1)
ACK?
Send LSB of
EEPROM Address
(1)
Send Data Byte
(2)
BYTE_COUNT
BYTE_COUNT+1
BYTE_COUNT =
T_BYTE?
Send Stop Condition
PAGE_COUNT
PAGE_COUNT+1
PAGE_COUNT =
T_PAGE?
Yes
No
No
No
Yes
No
Send Start Condition
Send Device Address
($A7)
END
ACK?
Yes
No
ACK?
Yes
No
ACK?
Yes
No
Yes
SER_EN High
Low-power (Standby)
Power-Cycle EEPROM
(Latches 1st Byte for
FPGA Download
Operations)
1st Data Byte
Value Changed Due
to Write?
No
Verify Final Write
Cycle Completion
Yes
Middle Byte
EEPROM Address
ACK?
No
Yes
8
AT94S Secure Family
2314D–FPSLI–2/04
Programming Summary:
Read from Whole Device
SER_EN Low
START
Send Start Condition
Send Device Address
($A6)
ACK?
Send MSB of
EEPROM Address
(1)
ACK?
Send LSB of
EEPROM Address
(1)
Send Start condition
BYTE_COUNT 0
Send Device Address
($A7)
Yes
No
No
Read Data Byte
(2)
BYTE_COUNT
BYTE_COUNT+1
Send ACK
END
BYTE_COUNT=
TT_BYTE?
No
ACK?
Yes
No
Yes
Sent Stop Condition
SER_EN High
Low-power (Standby)
Sequential Read from Current Address
ACK?
No
Yes
Yes
Random Access Setup
Middle Byte
EEPROM Address
ACK?
No
Yes
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB
EEPROM Address is Defined as:
TT_BYTE
AT17LV010 00 00 00 \h
AT17LV010 131072 \d
cSDA
cSCK
cSDA
cSCK
SAMPLE DATA BIT
STOP CONDITION
START CONDITION
cSDA
cSCK
ACK BIT
cSDA
cSCK
ACK
9
AT94S Secure Family
2314D–FPSLI–2/04
The organization of the Data Byte is shown above. Note that in this case, the Data Byte
is clocked into the device LSB first and MSB last.
Writing Writing to the normal address space takes place in pages. A page is 128-bytes long in
the 1-Mbit part. The page boundaries are, respectively, addresses where A
E0
down to
A
EOS
are all zero, and A
E6
down to A
E0
are all zero. Writing can start at any address
within a page and the number of bytes written must be 128 for the 1-Mbit part. The first
byte is written at the transmitted address. The address is incremented in the Configura-
tor following the receipt of each Data Byte. Only the lower 7 bits of the address are
incremented. Thus, after writing to the last byte address within the given page, the
address will roll over to the first byte address of the same page. A Write Instruction con-
sists of:
a Start Condition
a Device Address Byte with R/W
= 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge Bit from the Configurator
One or more Data Bytes (sent to the
Configurator)
Each followed by an Acknowledge Bit from the
Configurator
a Stop Condition
WRITE POLLING: On receipt of the Stop Condition, the Configurator enters an inter-
nally-timed write cycle. While the Configurator is busy with this write cycle, it will not
acknowledge any transfers. The programmer can start the next page write by sending
the Start Condition followed by the Device Address, in effect polling the Configurator. If
this is not acknowledged, then the programmer should abandon the transfer without
asserting a Stop Condition. The programmer can then repeatedly initiate a write instruc-
tion as above, until an acknowledge is received. When the Acknowledge Bit is received,
the write instruction should continue by sending the first EEPROM Address Byte to the
Configurator.
An alternative to write polling would be to wait a period of t
WR
before sending the next
page of data or exiting the programming mode. All signals must be maintained during
the entire write cycle.
Data Byte
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
1st 2nd 3rd 4th 5th 6th 7th 8th

AT94S40AL-25BQC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Field Programmable Gate Array ASICS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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