2014 Microchip Technology Inc. DS20005134B-page 19
SST25PF040B
TABLE 5-5: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
N
END
1
Endurance 10,000 Cycles JEDEC Standard A117
T
DR
1
Data Retention 100 Years JEDEC Standard A103
I
LTH
1
Latch Up 100+I
DD
mA JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-6: AC OPERATING CHARACTERISTICS 2.3-2.7V
Symbol
25 MHz 50 MHz
Parameter Min Max Min Max Units
F
CLK
1
1. Maximum clock frequency for Read instruction, 03H, is 25 MHz
Serial Clock Frequency 25 50 MHz
T
SCKH
Serial Clock High Time 18 9 ns
T
SCKL
Serial Clock Low Time 18 9 ns
T
SCKR
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
T
SCKF
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
T
CES
2
2. Relative to SCK
CE# Active Setup Time 55ns
T
CEH
2
CE# Active Hold Time 55ns
T
CHS
2
CE# Not Active Setup Time 55ns
T
CHH
2
CE# Not Active Hold Time 55ns
T
CPH
CE# High Time 50 50 ns
T
CHZ
CE# High to High-Z Output 77ns
T
CLZ
SCK Low to Low-Z Output 00ns
T
DS
Data In Setup Time 22ns
T
DH
Data In Hold Time 44ns
T
HLS
HOLD# Low Setup Time 55ns
T
HHS
HOLD# High Setup Time 55ns
T
HLH
HOLD# Low Hold Time 55ns
T
HHH
HOLD# High Hold Time 55ns
T
HZ
HOLD# Low to High-Z Output 77ns
T
LZ
HOLD# High to Low-Z Output 77ns
T
OH
Output Hold from SCK Change 00ns
T
V
Output Valid from SCK 12 8 ns
T
SE
Sector-Erase 25 25 ms
T
BE
Block-Erase 25 25 ms
T
SCE
Chip-Erase 50 50 ms
T
BP
Byte-Program 10 10 µs
SST25PF040B
DS20005134B-page 20 2014 Microchip Technology Inc.
FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM
TABLE 5-7: AC OPERATING CHARACTERISTICS 2.7-3.6V
Symbol
33 MHz 80 MHz
Parameter Min Max Min Max Units
F
CLK
1
Serial Clock Frequency 33 80 MHz
T
SCKH
Serial Clock High Time 13 6 ns
T
SCKL
Serial Clock Low Time 13 6 ns
T
SCKR
2
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
T
SCKF
Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
T
CES
3
CE# Active Setup Time 55ns
T
CEH
3
CE# Active Hold Time 55ns
T
CHS
3
CE# Not Active Setup Time 55ns
T
CHH
3
CE# Not Active Hold Time 55ns
T
CPH
CE# High Time 50 50 ns
T
CHZ
CE# High to High-Z Output 77ns
T
CLZ
SCK Low to Low-Z Output 00ns
T
DS
Data In Setup Time 22ns
T
DH
Data In Hold Time 44ns
T
HLS
HOLD# Low Setup Time 55ns
T
HHS
HOLD# High Setup Time 55ns
T
HLH
HOLD# Low Hold Time 55ns
T
HHH
HOLD# High Hold Time 55ns
T
HZ
HOLD# Low to High-Z Output 77ns
T
LZ
HOLD# High to Low-Z Output 77ns
T
OH
Output Hold from SCK Change 00ns
T
V
Output Valid from SCK 10 6 ns
T
SE
Sector-Erase 25 25 ms
T
BE
Block-Erase 25 25 ms
T
SCE
Chip-Erase 50 50 ms
T
BP
Byte-Program 10 10 µs
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz
2. Maximum Rise and Fall time may be limited by T
SCKH
and T
SCKL
requirements
3. Relative to SCK.
HIGH-Z
HIGH-Z
CE#
SO
SI
SCK
MSB
LSB
T
DS
T
DH
T
CHH
T
CES
T
CEH
T
CHS
T
SCKR
T
SCKF
T
CPH
25134 SerIn.0
2014 Microchip Technology Inc. DS20005134B-page 21
SST25PF040B
FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 5-3: HOLD TIMING DIAGRAM
25134 SerOut.0
CE#
SI
SO
SCK
MSB
T
CLZ
T
V
T
SCKH
T
CHZ
T
OH
T
SCKL
LSB
T
HZ
T
LZ
T
HHH
T
HLS
T
HLH
T
HHS
25134 Hold.0
HOLD#
CE#
SCK
SO
SI

SST25PF040B-80-4C-S2AE-T

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash
Lifecycle:
New from this manufacturer.
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