1
®
FN6140.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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MS82C55A, MQ82C55A, MP82C55A
CMOS Programmable Peripheral Interface
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV).
The MX82C55A has identical features as the X82C55 with
the exception of no bus hold devices on the port pins. It is a
general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in two groups of
12 and used in three major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
Features
Pb-Free Plus Anneal Available (RoHS Compliant)
(See Ordering Info)
Pin Compatible with OKI MSM82C55A
- No Bus Hold Devices on any Port Pins
24 Programmable I/O Pins
Fully TTL Compatible
High Speed, No “Wait State” Operation with 8MHz 80C86
and 80C88
Direct Bit Set/Reset Capability
Enhanced Control Word Read Capability
L7 Process
2.5mA Drive Capability on All I/O Ports
Low Standby Power (ICCSB). . . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART
NUMBERS*
(Note)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
CMP82C55AZ CMP82C55AZ 0 to 70 40 Ld PDIP** E40.6
CMS82C55AZ CMS82C55AZ 0 to 70 44 Ld PLCC N44.65
IMS82C55AZ IMS82C55AZ -40 to 85
CMQ82C55AZ CMQ82C55AZ 0 to 70 44 Ld MQFP Q44.10x10
IMQ82C55AZ IMQ82C55AZ -40 to 85
*Add “96” suffix to part number for tape and reel packaging.
**Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet June 15, 2006
2
FN6140.2
June 15, 2006
Pinouts
MS82C55A (PLCC)
TOP VIEW
MQ82C55A (MQFP)
TOP VIEW
CMP82C55A (PDIP)
TOP VIEW
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
RD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
WR
NC
PC2
NC
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
2827
123456
262524232221201918
7
8
9
10
11
12
13
14
15
16
17
PC6
PC7
A0
A1
GND
CS
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
PC5
PC4
PC0
PC1
PC2
28
27
26
25
24
23
2221201918
PB7
V
CC
D7
D6
D5
D4
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
NC
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
RD
PA0
PA1
PA2
PA3
NC
PB3
PB4
PB5
PB6
NC
NC
PC3
PB0
PB1
PB2
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
V
CC
PB7
PB6
PB5
PB4
PB3
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
MS82C55A, MQ82C55A, MP82C55A
3
FN6140.2
June 15, 2006
Functional Diagram
Pin Description
SYMBOL TYPE DESCRIPTION
V
CC
V
CC
: The +5V power supply pin. A 0.1µF capacitor between V
CC
and GND is recommended for decoupling.
GND GROUND
D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode.
CS
I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
RD
I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WR
I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
A0-A1 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PA0-PA7 I/O PORT A: 8-bit input and output port.
PB0-PB7 I/O PORT B: 8-bit input and output port.
PC0-PC7 I/O PORT C: 8-bit input and output port.
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
GROUP B
CONTROL
GROUP A
CONTROL
DATA BUS
BUFFER
READ
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-D0
POWER
SUPPLIES
+5V
GND
BIDIRECTIONAL
DATA BUS
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
8-BIT
INTERNAL
DATA BUS
FIGURE 1. FUNCTIONAL DIAGRAM
MS82C55A, MQ82C55A, MP82C55A

IMQ82C55AZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Interface - I/O Expanders PERI PRG-I/O 5V 8MHZ INDOKIPLACEMENT
Lifecycle:
New from this manufacturer.
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