19
FN6140.2
June 15, 2006
AC Electrical Specifications V
CC
= +5V± 10%, GND = 0V; T
A
= Operating Temperature Range
SYMBOL PARAMETER
TEST
CONDITIONS
82C55A
UNITSMIN MAX
READ TIMING
(1) tAR Address Stable Before RD
0-ns
(2) tRA Address Stable After RD
0-ns
(3) tRR RD Pulse Width 150 - ns
(4) tRD Data Valid From RD
1 - 120 ns
(5) tDF Data Float After RD
21075ns
(6) tRV Time Between RDs and/or WRs 300 - ns
WRITE TIMING
(7) tAW Address Stable Before WR
0-ns
(8) tWA Address Stable After WR 20 - ns
(9) tWW WR
Pulse Width 100 - ns
(10) tDW Data Valid to WR
High 100 - ns
(11) tWD Data Valid After WR High 30 - ns
OTHER TIMING
(12) tWB WR
= 1 to Output 1 - 350 ns
(13) tIR Peripheral Data Before RD
0-ns
(14) tHR Peripheral Data After RD 0-ns
(15) tAK ACK Pulse Width 200 - ns
(16) tST STB Pulse Width 100 - ns
(17) tPS Peripheral Data Before STB High 20 - ns
(18) tPH Peripheral Data After STB High 50 - ns
(19) tAD ACK = 0 to Output 1 - 175 ns
(20) tKD ACK = 1 to Output Float 2 20 250 ns
(21) tWOB WR
= 1 to OBF = 0 1 - 150 ns
(22) tAOB ACK = 0 to OBF = 1 1 - 150 ns
(23) tSIB STB = 0 to IBF = 1 1 - 150 ns
(24) tRIB RD
= 1 to IBF = 0 1 - 150 ns
(25) tRIT RD
= 0 to INTR = 0 1 - 200 ns
(26) tSIT STB = 1 to INTR = 1 1 - 150 ns
(27) tAIT ACK = 1 to INTR = 1 1 - 150 ns
(28) tWIT WR
= 0 to INTR = 0 1 - 200 ns
(29) tRES Reset Pulse Width 1, (Note) 500 - ns
NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum.
MS82C55A, MQ82C55A, MP82C55A
20
FN6140.2
June 15, 2006
Timing Waveforms
FIGURE 25. MODE 0 (BASIC INPUT)
FIGURE 26. MODE 0 (BASIC OUTPUT)
FIGURE 27. MODE 1 (STROBED INPUT)
tRA (2)
tHR (14)
tRR (3)
tIR (13)
tAR (1)
tRD (4) tDF (5)
RD
INPUT
CS
, A1, A0
D7-D0
tAW (7)
tWA (8)
tWS (12)
tWW (9)
tWD (11)
tDW
WR
D7-D0
CS
, A1, A0
OUTPUT
(10)
tST (16)
STB
INTR
RD
INPUT FROM
IBF
PERIPHERAL
tSIB
tSIT
tPH
tPS (17)
tRIT
tRIB (24)
(23)
(26)
(25)
(18)
MS82C55A, MQ82C55A, MP82C55A
21
FN6140.2
June 15, 2006
FIGURE 28. MODE 1 (STROBED OUTPUT)
FIGURE 29. MODE 2 (BIDIRECTIONAL)
NOTE: Any sequence where WR
occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD + OBF MASK
ACK
WR)
Timing Waveforms (Continued)
tWOB (21)
tWB (12)
tAK (15) tAIT (27)
tAOB (22)
tWIT
OBF
WR
INTR
ACK
OUTPUT
(28)
tWOB
tAOB
tAK
tAD (19)
tKD
tPH (18)
tPS (17)
tSIB
tST
OBF
WR
INTR
ACK
IBF
STB
PERIPHERAL
BUS
RD
tRIB (24)
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
DATA FROM
CPU TO 82C55A
(21)
(22)
(15)
(16)
(20)
(23)
(NOTE)
(NOTE)
MS82C55A, MQ82C55A, MP82C55A

IMQ82C55AZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Interface - I/O Expanders PERI PRG-I/O 5V 8MHZ INDOKIPLACEMENT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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