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LE25U20AMB-AH

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
LE25U20AMB
www.onsemi.com
13
10. Silicon ID Read
Silicon ID read is an operation that reads the manufacturer code and device code information. The silicon ID read
command is not accepted during writing.
Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is
completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h, 2 bytes of
device ID code (Memory type, Memory capacity) and reserved code are repeatedly output in succession so long as
the clock input is continued. Refer to "Figure 16-a Silicon ID Read 1" for the waveforms. "Table 6_1 Silicon ID
Read 1" lists the silicon ID read1 codes.
The second method involves inputting the ABh command. This command consists of the first through fourth bus
cycles, and the 1 byte silicon ID can be read when 24 dummy bits are input after (ABh). Refer to "Figure 16-b
Silicon ID Read 2" for the waveforms. "Table 6_2 Silicon ID Read 2" lists the silicon ID read2 code. If, after the
device code has been read, the SCK input is continued, the device code is output repeatedly.
The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the
rising CS
edge.
Table 6_1 Silicon ID Read 1 Table 6_2 Silicon ID Read 2
Figure 16-a Silicon ID Read 1
Figure 16-b Silicon ID Read 2
CS
High Impedance
44h 44h
SCK
SO
SI
A
Bh X X X
15
MSB MSB
0 1 2 3
4 5 6 7 8 2316 24 31 39
8CLK
Mode0
Mode3
32
Output Code
Manufacturer code 62h
2Byte
Device ID
Memory Type 06h
Memory Capacity
code
12h(2MBit)
Reserved code 00h
CS
High Impedance
12h 06h 62h
SCK
SO
SI
9Fh
15
MSB MSB MSB
0 1 2 3
4 5 6 7 8 2316
8CLK
Mode0
Mode3
24
31
32
39
06h
00h
MSB MSB
Output Code
1Byte
Device ID
44h
LE25U20AMB
www.onsemi.com
14
11. Hold Function
Using the HOLD
pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17
HOLD
" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the
logic level of SCK is low, and it exits from the hold status at the rising HOLD
edge. When the logic level of SCK is
high, HOLD
must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is
exited and serial communication is reset at the rising CS
edge. In the hold status, the SO output is in the high-
impedance state, and SI and SCK are "don't care".
Figure 17 HOLD
12. Power-on
In order to protect against unintentional writing, CS
must be kept at V
CC
At power-on. After power-on, the supply
voltage has stabilized at 2.30 V or higher, wait for 100 s (t
PU
_READ) before inputting the command to start a read
operation. Similarly, wait for 10ms (t
PU
_WRITE) after the voltage has stabilized before inputting the command to
start a write operation.
Figure 18 Power-on Timing
CS
HOLD
SCK
SO
A
ctive
HOLD
A
ctive
t
HH
t
HS
t
HLZ
t
HHZ
High Impedance
t
HH
t
HS
V
DD
(Max)
V
DD
(Min)
V
DD
Chip selection not Allowed
0V
t
PU
_WRITE
t
PU
_READ
Program, Erase and Write Command not Allowed
Read Access Allowed
Full Access Allowed
LE25U20AMB
www.onsemi.com
15
13. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25U20AMB incorporates a power-on reset
function. The following conditions must be met in order to ensure that the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19 Power-down Timing
14. Software Data Protection
The LE25U20AMB eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS
edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1 F ceramic capacitor must be provided to each device and connected between V
DD
and V
SS
in order to
ensure that the device will operate stably.
V
DD
(Max)
V
DD
(Min)
V
DD
No Device Access Allowed
0V
vBOT
t
PU
_WRITE
t
PU
_READ
t
PD
Program, Erase and Write Command not Allowed
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

LE25U20AMB-AH

Mfr. #:
Buy LE25U20AMB-AH
Manufacturer:
ON Semiconductor
Description:
NOR Flash S-FLASH MEMORY(2M)
Lifecycle:
New from this manufacturer.
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