LE25U20AMB
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4
Device Operation
The LE25U20AMB features electrical on-chip erase functions using a single 2.5 V power supply, that have been
added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are
facilitated by incorporating the command registers inside the chip. The read, erase, program and other required
functions of the device are executed through the command registers. The command addresses and data input in
accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required
operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling
CS
edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are
introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time,
output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is
output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and
silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing.
The LE25U20AMB supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS
edge, SPI mode 0
is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level
of SCK is high.
Table 2 Command Settings
Command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle Nth bus cycle
Read
03h A23-A16 A15-A8 A7-A0
0Bh A23-A16 A15-A8 A7-A0 X
Small sector erase
D7h/20h A23-A16 A15-A8 A7-A0
Sector erase
D8h A23-A16 A15-A8 A7-A0
Chip erase
C7h
Page program
02h A23-A16 A15-A8 A7-A0 PD * PD * PD *
Write enable
06h
Write disable
04h
Power down
B9h
Status register read
05h
Status register write
01h DATA
Read silicon ID 1
9Fh
Read silicon ID 2
ABh X X X
Exit power down mode
ABh
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A18 for all commands are "Don't care".
In order for commands other than the read command to be recognized, CS
must rise after all the bus cycle input.
*: "PD" stands for page program data.
LE25U20AMB
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5
Figure 3 Serial Input Timing
Figure 4 Serial Output Timing
High Impedance
t
DH
t
CPH
t
DS
t
CSH
t
CSS
CS
DATA VALID
SO
SI
SCK
High Impedance
t
CSS
t
CSH
t
CLHI
t
CLLO
t
HO
t
CHZ
t
CLZ
SI
t
V
CS
SO
SCK
DATA VALID
LE25U20AMB
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6
Description of Commands and Their Operations
"Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions
and operations corresponding to each command is presented below.
1. Read
There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first
through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in
the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of
fourth bus cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms.
Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8
dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands
is whether the dummy bits in the fifth bus cycle are input.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the
highest address (3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued.
By setting the logic level of CS
to high, the device is deselected, and the read cycle ends. While the device is
deselected, the output pin SO is in a high-impedance state.
Figure 5-a 4 Bus Read
Figure 5-b 5 Bus Read
N+2 N+1 N
CS
High Impedance
DATA DATA DATA
SCK
SO
SI
03h
A
dd.
A
dd.
A
dd.
15
MSB MSB MSB
0 1 2 3 4 5 6 7 8 23 16 24 31 39 47
8CLK
Mode0
Mode3
32 40
N+2 N+1 N
CS
High Impedance
DATA DATA DATA
SCK
SO
SI
0Bh
A
dd.
A
dd.
A
dd. X
15
MSB MSB MSB
0 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 47 48 55
Mode3
Mode0
8CLK

LE25U20AMB-AH

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
NOR Flash S-FLASH MEMORY(2M)
Lifecycle:
New from this manufacturer.
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