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NCV7361AD

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV7361A
http://onsemi.com
19
MIN/MAX SLOPE TIME CALCULATION
Figure 27. Slope Time Calculation
95%
100%
0%
t
srec
t
sdom
V
BUS
40%
V
dom
60%
5%
BUS
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dVńdt + 0.2 * V
swing
ń(t
40%
−t
60%
)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
t
slope
+ 5*(t
40%
−t
60%
)
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
t
slope
+ V
swing
ńdVńdt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because
it’s a passive edge. In case of low battery voltages and high
bus loads the rising edge is only determined by the network.
If the rising edge slew rate exceeds the value of the
dominant one, the slew rate control determines the rising
edge.
Power Dissipation and Operating Range
The max power dissipation depends on the thermal
resistance of the package and the PCB, the temperature
difference between Junction and Ambient as well as the
airflow.
The power dissipation can be calculated with:
P
D
+ (V
SUP
* V
OUT
)*I
VOUT
) P
D_TX
The power dissipation of the transmitter P
D_TX
depends
on the transceiver configuration and its parameters as well
as on the bus voltage V
BUS
= V
BAT
− V
D
, the resulting
termination resistance R
L
, the capacitive bus load C
L
and
the bit rate. Figure 28 shows the dependence of power
dissipation of the transmitter as function of V
SUP
. The
conditions for calculation the power dissipation was:
R
L
= 500 W, C
L
= 10 nF, Bitrate = 20 kbit and duty cycle
on TxD of 50%.
Figure 28. Power Dissipation LIN Transceiver
@ 20 kbit
5
50
17
40
181514
V
SUP
(V)
P
D
(mW)
30
10
0
616197
20
45
35
25
5
15
1312111089
The permitted package power dissipation can be
calculated:
P
Dmax
+
T
J
* T
A
R
qJ
−
A
If we consider that P
D_TX_max
= f(V
SUP
), it can be
calculated the max output current IV
OUT
on V
OUT
:
I
VOUTmax
+
T
J
−T
A
R
qJ
−
A
* P
D_TX_max
@ VSUP
VSUP * VOUT
T
J
−T
A
is the temperature difference between junction
and ambient, and R
th
is the thermal resistance of the
package. The thermal energy is transferred via the package
and the pins to the ambient. This transfer can be improved
with additional ground areas on the PCB as well as ground
areas under the IC.
NCV7361A
http://onsemi.com
20
Table 1. SO−8 Thermal RC Network Models*
Copper Area (1 oz thick) 54 mm
2
714 mm
2
54 mm
2
714 mm
2
(SPICE Deck Format) Cauer Network Foster Network
54 mm
2
714 mm
2
Units Tau Tau Units
C_C1 Junction GND 1.08E−05 1.08E−05 W−s/C 1.00E−06 1.00E−06 sec
C_C2 node1 GND 4.10E−05 4.10E−05 W−s/C 1.00E−05 1.00E−05 sec
C_C3 node2 GND 1.13E−04 1.13E−04 W−s/C 1.00E−04 1.00E−04 sec
C_C4 node3 GND 4.42E−04 4.40E−04 W−s/C 5.00E−04 5.00E−04 sec
C_C5 node4 GND 1.74E−03 1.71E−03 W−s/C 1.00E−03 1.00E−03 sec
C_C6 node5 GND 1.39E−03 1.34E−03 W−s/C 1.00E−02 1.00E−02 sec
C_C7 node6 GND 2.08E−02 1.78E−02 W−s/C 1.00E−01 1.00E−01 sec
C_C8 node7 GND 1.08E−02 9.75E−03 W−s/C 1.00E+00 1.00E+00 sec
C_C9 node8 GND 1.14E−01 1.84E−01 W−s/C 1.00E+01 1.00E+01 sec
C_C10 node9 GND 8.11E−01 3.00E+00 W−s/C 5.00E+01 5.00E+01 sec
R’s R’s
R_R1 Junction node1 0.119 0.119 C/W 0.070 0.070 C/W
R_R2 node1 node2 0.286 0.286 C/W 0.152 0.152 C/W
R_R3 node2 node3 0.857 0.859 C/W 0.481 0.481 C/W
R_R4 node3 node4 1.181 1.189 C/W 0.690 0.690 C/W
R_R5 node4 node5 1.241 1.276 C/W 0.584 0.584 C/W
R_R6 node5 node6 2.574 2.690 C/W 3.223 3.223 C/W
R_R7 node6 node7 18.065 21.708 C/W 0.823 0.823 C/W
R_R8 node7 node8 27.965 26.035 C/W 26.801 35.166 C/W
R_R9 node8 node9 80.896 49.821 C/W 63.710 52.538 C/W
R_R10 node9 GND 49.468 15.252 C/W 86.119 25.510 C/W
*Bold face items in the tables above represent the package without the external thermal system.
The Cauer networks generally have physical
significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Cauer networks can be easily implemented using circuit
simulating tools, whereas Foster networks may be more
easily implemented using mathematical tools (for instance,
in a spreadsheet program), according to the following
formula:
R(t) +
n
S
i + 1
R
i
ǒ
1−e
−tńtau
i
Ǔ
Junction
Ambient
(thermal ground)
R
1
R
2
C
1
C
2
C
3
C
n
R
n
R
3
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Figure 29. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Figure 30. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
Junction
Ambient
(thermal ground)
R
1
R
2
C
1
C
2
C
3
C
n
R
n
R
3
Each rung is exactly characterized by its RC−product time constant; Am-
plitudes are the resistances
NCV7361A
http://onsemi.com
21
100
110
120
0 100 200 300 400 500 600 800
2.0 oz. Cu
Figure 31. SO−8, q
JA
as a Function of the Pad Copper Area Including Traces,
Board Material
q
JA
(°C/W)
130
140
150
160
170
180
190
Copper Area (mm
2
)
1.0 oz. Cu
700
0.01
1
10
100
1000
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 32. SO−8 Thermal Transient Response on Typical Test Boards
Cu Area = 53.9 mm
2
1.0 oz.
Cu Area = 713.9 mm
2
1.0 oz.
R
q
(°C/W)
0.1
Cu Area = 89.7 mm
2
1.0 oz.
0.01
1
10
1000
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 33. SO−8 Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board
50% Duty Cycle
Single Pulse
10%
5%
2%
1%
Duty Cycle, D =
t
1
t
2
P
DM
Notes:
t
1
t
2
R
q
(°C/W)
EFFECTIVE THERMAL RESISTANCE
Cu Area = 713.9 mm
2
1.0 oz.
100
0.1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV7361AD

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Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators LDO REG w/Integrated
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