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NCV7361AD

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV7361A
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (5.25 V v V
SUP
v 18 V, −40°C v T
A
v 125°C unless otherwise noted)
Characteristic
Symbol Condition Min Typ Max Unit
V
SUP
Supply Current with V
OUT
“No Load’’ (Note 4)
I
Snl
V
EN
= V
SUP
= 12 V, V
BUS
>
V
SUP
− 0.5 V, Pins 5 to 8 Open
− − 110 mA
Supply Current, “Sleep Mode’’ I
Ssleep
V
SUP
= 12 V, V
EN
= 0 V, V
BUS
>
V
SUP
− 0.5 V
− 35 50 mA
Thermal Shutdown (Note 5) T
JSHD
− 155 − 175 °C
Thermal Recovery (Note 5) T
Jrec
− 126 − 130 °C
V
SUP
Undervoltage Reset “OFF” V
SUVR_OFF
V
SUP
Ramp Up − 3.5 3.9 V
V
SUP
Undervoltage Reset “ON” V
SUVR_ON
V
SUP
Ramp Down − 3.0 3.3 V
V
SUP
Undervoltage Hysteresis V
SUVR_HYS
V
SUVR_OFF
− V
SUVR_ON
0.2 − − V
Operating Voltage V
SUP
5.25 12 18 V
V
OUT
Output Voltage V
OUTt
5.5 V v V
SUP
v 18 V
0 < I
OUT
< 50 mA
4.90 5.0 5.10 V
V
OUTh
V
SUP
> 18 V 4.90 5.0 5.25 V
V
OUTl
IV
OUT
= 20 mA, V
SUP
= 3.3 V − V
SUP
−V
D
− V
IV
OUT
= 50 mA, V
SUP
= 3.3 V − V
SUP
−V
D
− V
Drop−Out Voltage (Note 6)
V
D
= V
SUP
−V
OUT
V
D
IV
OUT
= 20 mA − − 150 mV
IV
OUT
= 50 mA − − 500 mV
Output Current IV
OUT
3.0 V < V
SUP
< 18 V
V
OUT
= 0 V
50 − 150 mA
Load Capacity C
load
Reference Figure 35 4.7 − − mF
ENABLE (EN)
Input Voltage Low V
ENL
− −0.3 − 1.6 V
Input Voltage High V
ENH
− 2.5 − V
SUP
+0.3
V
Hysteresis (Note 5) V
ENHYS
− 100 − − mV
Pulldown Current I
pdEN
V
EN
> V
ENH
1.0 4.0 7.0 mA
V
EN
< V
ENL
70 100 130 mA
RESET
Output Voltage Low V
OL
I
OUT
= 1.0 mA, V
SUP
> 5.5 V − − 0.8 V
10 kW RESET to V
OUT
V
SUP
= V
OUT
= 0.8 V
− − 0.2 V
Pullup Current I
pu
− −500 −375 −250 m A
RESET Threshold V
RES
Referred to V
OUT
, V
SUP
> 4.6 V 4.5 4.65 4.8 V
Master Reset Threshold (Note 5) V
MRes
− 3.0 3.15 3.3 V
4. See Figure 6 for test setup.
5. Not production tested, guaranteed by design and qualification.
6. Measured when the output voltage has dropped 100 mV from the V
SUP
= 12 V nominal value.
NCV7361A
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (5.25 V v V
SUP
v 18 V, −40°C v T
A
v 125°C unless otherwise noted)
Characteristic
Symbol Condition Min Typ Max Unit
LIN BUS INTERFACE
Receive Threshold
V
thr_rec
,
V
thr_dom
7.0 V v V
SUP
v 18 V
0.4 *V
SUP
− 0.6
*V
SUP
V
Receive Center Point
V
thr_cnt
= (V
thr_rec
+ V
thr_dom
)/2
V
thr_cnt
0.475
*V
SUP
0.5
*V
SUP
0.525
*V
SUP
Receive Hysteresis
V
thr_hys
= V
thr_rec
− V
thr_dom
V
thr_hys
0.12 *V
SUP
0.135
*V
SUP
0.15
*V
SUP
BUS Input Current (Recessive)
(Note 7)
I
INBUSR
8.0 v V
BUS
v 18 V,
V
SUP
= V
BUS
− 0.7 V, TxD = 4.5 V
− − 20 mA
BUS Input Current (Recessive) −I
INBUSR
V
SUP
= 0 V, V
BUS
= −12 V −1.0 − − mA
BUS Input Current (Recessive) −I
INBUSR
V
SUP
= Open, V
BUS
= −18 V −1.0 − − mA
BUS Pullup Resistor R
BUSpu
− 20 30 47 kW
BUS Output Voltage (Dominant)
(Note 7)
V
BUSdom
7.0 v V
SUP
v 18 V, TxD = 0 V,
R
L
= 500 W
− − 1.2 V
BUS Output Voltage (Recessive)
(Notes 7 and 8)
V
BUSrec
7.0 v V
SUP
v 18 V, TxD = 4.5 V 0.8 *V
SUP
− − V
BUS Current Limit I
LIM
V
BUS
> 2.5 V, TxD = 0 V 40 − 120 mA
TxD
Pullup Resistance R
pu_TxD
− 9.5 15 21 kW
Input Low Level V
IL
− − − 1.25 V
Input High Level V
IH
− 3.75 − − V
RxD
Output Voltage Low V
OL
I
OUT
= 1.0 mA − − 0.8 V
Output Voltage High V
OH
I
OUT
= −1.0 mA 4.2 − − V
7. See Figures 7, 8, and 9 for test setup.
8. The recessive voltage on BUS should not be less than 80% direct battery
.
The LIN specification requires an external reverse battery diode
between the battery and V
SUP
. V
SUP
= V
BAT
−0.7 V.
NCV7361A
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS (7.0 V v V
SUP
v 18 V, −40°C v T
A
v 125°C unless otherwise noted)
Characteristic Symbol Condition Min Typ Max Unit
RESET AC CHARACTERISTICS
Reset Time t
Res
− 50 100 140 ms
Reset Rise Time (Note 9) t
rr
− 3.0 7.5 15 ms
BUS Debounce Time (Note 14) t
deb_BUS
− 1.5 2.8 4.0 ms
Wake−Up Time t
Wake_BUS
− 25 60 120 ms
GENERAL LIN BUS INTERFACE AC CHARACTERISTICS
Transmit Propagation Delay
TxD −> BUS (Notes 10 and 11)
t
dr_TxD
,
t
df_TxD
R
L
/C
L
at BUS
1.0 kW/1.0 nF
660 W/6.8 nF
500 W/10 nF
V
SUPMIN
= 8 V
− − 4.0 ms
Symmetry of Propagation Delay
BUS −> RxD (Note 10)
t
dsym_TxD
t
dr_TxD
− t
df_TxD
V
SUPMIN
= 8 V
−2.0 − 2.0 ms
Receiver Propagation Delay
BUS −> RxD (Notes 10 and 11)
t
dr_RxD
t
df_RxD
C
L(RxD)
= 50 pF
V
SUPMIN
= 8 V
− − 6.0 ms
Symmetry of Propagation Delay
TxD −> BUS (Note 10)
t
dsym_RxD
t
dr_RxD
− t
df_RxD
V
SUPMIN
= 8 V
−2.0 − 2.0 ms
Slew Rate BUS Rising Edge (Note 9) dV/dT
rise
20% v V
BUS
v 80%
C
L
= 1.0 nF, R
L
= 1.0 kW
V
SUPMIN
= 8 V
1.0 1.7 2.5 V/ms
Slew Rate BUS Falling Edge (Note 9) dV/dT
fall
20% v V
BUS
v 80%
C
L
= 1.0 nF, R
L
= 1.0 kW
V
SUPMIN
= 8 V
−2.5 −1.7 −1.0 V/ms
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 1.3
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
t
sdom
V
SUP
= 8.0 V
R
L
= 500 W/C
L
= 10 nF
− − 12 ms
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
t
srec
V
SUP
= 8.0 V
R
L
= 500 W/C
L
= 10 nF
− − 12 ms
Slope Time Symmetry t
ssym
V
SUP
= 8.0 V
R
L
= 500 W/C
L
= 10 nF
T
ssym
= t
sdom
− t
srec
−7.0 − 1.0 ms
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
t
sdom
V
SUP
= 18 V
R
L
= 500 W/C
L
= 10 nF
− − 18 ms
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
t
srec
V
SUP
= 18 V
R
L
= 500 W/C
L
= 10 nF
− − 18 ms
Slope Time Symmetry t
ssym
V
SUP
= 18 V
R
L
= 500 W/C
L
= 10 nF
T
ssym
= t
sdom
− t
srec
−5.0 − 5.0 ms
9. Not production tested, guaranteed by design and qualification.
10. See Figures 2 and 3, Timing Diagrams.
11. See Figures 5, 6, 7, 8, and 9 for test setup.
12.t
sdom
= (t
VBUS40%
− t
VBUS95%
) / 0.55.
13.t
sdom
= (t
VBUS60%
− t
VBUS5%
) / 0.55.
14. See Figure 18.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV7361AD

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Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators LDO REG w/Integrated
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