SKY72301-22 Datasheet SKY72301-22 | P13-P15

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

200706C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 11, 2009 13

A3 A2 A1 A0 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 1 X X MSB LSB

Full Power Down

Main Synthesizer Power Down

Main Synthesizer Mode

Main Synthesizer ΔΣ Fractionality

Auxiliary Synthesizer Power Down

Auxiliary Synthesizer Mode

Multiplexer Output Selection

Mux_out Pin Tri-State Enable

C1424

Figure 13. Power Down/Multiplexer Output Select Control Register (Write Only)

Table 4. Multiplexer Output

Multiplexer Output Select

(Bit 8)

Multiplexer Output Select

(Bit 7)

Multiplexer Output Select

(Bit 6)

Multiplexer Output

(Mux_out)

0 0 0 Reference Oscillator

0 0 1 Auxiliary Reference Frequency (F

ref_aux

)

0 1 0 Main Reference Frequency (F

ref_main

)

0 1 1 Auxiliary Phase Detector Frequency (F

pd_aux

)

1 0 0 Main Phase Detector Frequency (F

pd_main

)

1 0 1 Serial data out

1 1 0 Serial interface test output

1 1 1 Unused

 Main Synthesizer  Fractionality = One-bit flag to configure

the size of the main  modulator. This has a direct effect on

power consumption and on the level of fractionality and step

size. When this bit is cleared, the main  modulator is 18-bit

with a fractionality of 218 and a step size of Fref_main/262144.

When this bit is set, the main  modulator is 10-bit with a

fractionality of 210 and a step size of Fref_main/1024.

 Auxiliary Synthesizer Power Down = One-bit value to power

down the auxiliary synthesizer. When this bit is cleared, the

auxiliary synthesizer is powered up. When this bit is set, the

auxiliary synthesizer is in power-down mode.

 Auxiliary Synthesizer mode = One-bit value to power down the

auxiliary synthesizer’s  modulator and fractional unit to

operate as an integer-N synthesizer. When this bit is cleared,

the auxiliary synthesizer is in fractional-N mode. When this bit is

set, the auxiliary synthesizer is in integer-N mode.

NOTE: There are no special power-up sequences required for the

SKY72301-22.

 Multiplexer Output Selection = Three-bit value that selects

which internal signal is output to the Mux_out pin. Internal

signals available on this pin are the following:

 Reference Oscillator, F

ref

 Main or auxiliary divided reference (post reference

frequency main or auxiliary dividers), F

ref_main

or F

ref_aux

 Main or auxiliary phase detector frequency (post main and

auxiliary frequency dividers), F

pd_main

or F

pd_aux

 Serial data out, for loop-back and test purposes

See Table 4 for more information.

 Mux_out Pin Tri-State Enable = One-bit flag to tri-state the

Mux_out pin. When this bit is cleared, the Mux_out pin is

enabled. When this bit is set, the Mux_out pin is tri-stated.

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

September 11, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200706C

A3 A2 A1 A0 11 10 9 8 7 6 5 4 3 2 1 0

1 0000000XX

Reserved Bits

Modulation Data Magnitude Offset

Modulation Data Input Select

Modulation Address Disable

C1425

Figure 14. Modulation Control Register (Write Only)

A3 A2 A1 A0 11 10 9 8 7 6 5 4 3 2 1 0

1001

MSB LSB

Modulation Data Bits

C1426

Figure 15. Modulation Data Register (Write Only)

The Modulation Control Register is used to configure the

modulation unit of the main synthesizer. The modulation unit adds

or subtracts a frequency offset to the selected center frequency at

which the main synthesizer operates. The size of the modulation

data sample, controlled by the duration of the CS signal, can be

from 2 to 12 bits wide, to provide from 4 to 4096 selectable

frequency offset steps.

The modulation data magnitude offset selects the magnitude

multiplier for the modulation data and can be from 0 to 8. As

shown in Figure 14, the values to be loaded are:

 Modulation Data Magnitude Offset = Four-bit value that

indicates the magnitude multiplier (m) for the modulation data

samples. Valid values range from 0 to 13, effectively providing a

multiplication of the modulation data sample.

 Modulation Data Input Select = One-bit flag to indicate the pin

on which modulation data samples are serially input when the

CS signal is between 2 and 12 bits long. When this bit is

cleared, modulation data samples are to be presented on the

Data pin. When this bit is set, modulation data samples are to

be presented on the Mod_in pin.

 Modulation Address Disable = One-bit flag to indicate the

presence of the address as modulation data samples are

presented on either the Mod_in or Data pins. When this bit is

cleared, the address is presented with the modulation data

samples (i.e., all transfers are 16 bits long). When this bit is set,

no address is presented with the modulation data samples (i.e.,

all transfers are 2 to 12 bits long).

The Modulation Data Register is used to load the modulation data

samples to the modulation unit. These values are transferred to

the modulation unit on the falling edge of F

pd_main

where they are

passed to the mainmodulator at the selected magnitude

offset on the next falling edge of F

pd_main

. Modulation Data register

values are 2's complement format. As shown in Figure 15, the

value to be loaded is:

 Modulation Data Bits = Modulation data samples that represent

the desired instantaneous frequency offset to the selected main

synthesizer frequency (selected channel) before being affected

by the modulation data magnitude offset.

Package and Handling Information

Since the device package is sensitive to moisture absorption, it is

baked and vacuum packed before shipping. Instructions on the

shipping container label regarding exposure to moisture after the

container seal is broken must be followed. Otherwise, problems

related to moisture absorption may occur when the part is

subjected to high temperature during solder assembly.

The SKY72301-22 is rated to Moisture Sensitivity Level 3 (MSL3)

at 260 C. It can be used for lead or lead-free soldering.

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

200706C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 11, 2009 15

Care must be taken when attaching this product, whether it is

done manually or in a production solder reflow environment.

Production quantities of this product are shipped in a standard

tape and reel format. For packaging details, refer to the Skyworks

Application Note, Tape and Reel, document number 101568.

Electrical and Mechanical Specifications

The SKY72301-22 is supplied as a 28-pin EP-TSSOP. The

exposed pad is located on the bottom side of the package and

must be connected to ground for proper operation. The exposed

pad should be soldered directly to the circuit board.

Signal pin assignments and functional pin descriptions are

specified in Table 5. The absolute maximum ratings of the

SKY72301-22 are provided in Table 6. The recommended

operating conditions are specified in Table 7 and electrical

specifications are provided in Table 8.

Figure 16 provides a schematic diagram for the SKY72301-22.

Figure 17 shows the package dimensions for the 28-pin

EP-TSSOP and Figure 18 provides the tape and reel dimensions.

Table 5. SKY72301-22 Signal Descriptions (1 of 2)

Pin # Pin Name Type Description

1 Clock Digital input Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the

Data pin on the rising edge of Clock.

2 Mod_in Digital input Alternate serial modulation data input pin. Address bits are followed by data bits.

3 Mux_out Digital output Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main

or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be tri-stated from

the synthesizer registers.

4 VSUBdigital – Substrate isolation. Connect to ground.

5 GNDecl/cml (Note 1) Power and ground Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground.

6 VCCcml_main

(Note 1)

Power and ground ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump.

7 Fvco_main Input Main VCO differential input.

8 Fvco_main Input Main VCO complimentary differential input.

9 LD/PSmain Analog output Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open

collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This

pin is configured using the Phase Detector/Charge Pumps Control Register.

10 VCCcp_main

(Note 1)

Power and ground Main charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain

and charge pump.

11 CPout_main Analog output Main charge pump output. The gain of the main charge pump phase detector is controlled by the Phase

Detector/Charge Pumps Control Register.

12 GNDcp_main

(Note 1)

Power and ground Main charge pump ground.

13 Xtalacgnd/OSC Ground/input Reference crystal AC ground or external oscillator differential input.

14 Xtalin/OSC Input Reference crystal input or external oscillator differential input.

15 Xtalout/NC Input Reference crystal output or no connect.

16 VCCxtal Power and ground Crystal oscillator ECL/CML, 3 V.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

SKY72301-22

Mfr. #:

Buy SKY72301-22

Manufacturer:

Skyworks Solutions, Inc.

Description:

Phase Locked Loops - PLL 1GHz / 500MHz Syn. Phase noise-96dBc/Hz

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New from this manufacturer.

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