SKY72301-22 Datasheet SKY72301-22 | P4-P6

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

September 11, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200706C

Serial Interface Operation

The serial interface consists of three signals: Clock (pin 1), Data

(pin 27) and CS (pin 28). The Clock signal controls data on the two

serial data lines (Data and CS). The Data pin bits shift into a

temporary register on the rising edge of Clock. The CS line allows

individual selection transfers that synchronize and sample the

information of slave devices on the same bus.

Figure 3 functionally depicts how a serial transfer takes place.

A serial transfer is initiated when a microcontroller or

microprocessor forces the CS line to a low state. This is followed

immediately by an address/data stream sent to the Data pin that

coincides with the rising edges of the clock presented on the

Clock line.

Each rising edge of the Clock signal shifts in one bit of data on the

Data line into a shift register. At the same time, one bit of data is

shifted out of the Mux_out pin (if the serial bit stream is selected)

at each falling edge of Clock. To load any of the registers, 16 bits

of address or data must be presented to the Data line with the

LSB last while the CS signal is low. If the CS signal is low for

more than 16 clock cycles, only the last address or data bits are

used to load the registers.

If the CS signal is brought to a high state before the 13

Clock

edge, the bit stream is assumed to be modulation data samples.

In this case, it is assumed that no address bits are present and

that all the bits in the stream should be loaded into the

Modulation Data Register.

the following variables and constants:

fractional

Desired VCO division ratio in fractional-N applications.

This is a real number and can be interpreted as the

reference frequency (F

ref

) multiplying factor such that

the resulting frequency is equal to the desired VCO

frequency.

integer

Desired VCO division ratio in integer-N applications.

This number is an integer and can be interpreted as

the reference frequency (F

ref

) multiplying factor so that

the resulting frequency is equal to the desired VCO

frequency.

reg

Nine-bit unsigned input value to the divider ranging

from 0 to 511 (integer-N mode) and from 6 to 505

(fractional-N mode).

divider This constant equals 262144 when the  modulator

is in 18-bit mode, and 1024 when the  modulator is

in 10-bit mode.

dividend When in 18-bit mode, this is the 18-bit signed input

value to the  modulator, ranging from

–131072 to +131071 and providing 262144 steps,

each step equal to F

div_ref

Hz.

When in 10-bit mode, this is the 10-bit signed input

value to the  modulator, ranging from

–512 to +511 and providing 1024 steps, each step

equal to Fdiv_ref/2

Hz.

VCO

Desired VCO frequency (either F

vco_main

or F

vco_aux

div_ref

Divided reference frequency presented to the phase

detector (either F

ref_main

or F

ref_aux

X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX

Clock

Last

Data

C1413

Figure 3. Serial Transfer Timing Diagram

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

200706C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 11, 2009 5

Fractional-N Applications. The desired division ratio for the

main and auxiliary synthesizer is given by the following equation:

f rac tio nal

VCO

div_ref

-- --- --- ------ --- --=

where N

fractional

must be between 37.5 and 537.5.

The value to be programmed by the Main or Auxiliary Divider

reg

Round N

fr actio nal

32–=

NOTE: The Round function rounds the number to the nearest

integer.

When in fractional mode, allowed values for N

reg

are from 6 to

505, inclusive.

The value to be programmed by either of the MSB/LSB Dividend

registers or the Auxiliary Dividend Register is given by the

following equation:

dividend Round divider N

fra ctio nal

reg

32–– =

where the divider is either 1024 in 10-bit mode or 262144 in

18-bit mode. Therefore, the dividend is a signed binary value

either 10 or 18 bits long.

NOTE: Because of the high fractionality of the SKY72301-22,

there is no practical need for any integer relationship

between the reference frequency and the channel spacing

or desired VCO frequencies.

Sample calculations for two fractional-N applications are provided

in Figure 4.

Integer-N Applications. The desired division ratio for the main or

auxiliary synthesizer is given by:

integer

VCO_main

div_ref

- --- ------ ------ ------ ------=

where N

integer

is an integer number from 32 to 543.

The value to be programmed by the Main or Auxiliary Divider

reg

integer

32–=

When in integer mode, allowed values for N

reg

are from 0 to 511

for both the main and auxiliary synthesizers.

NOTE

: As with all integer-N synthesizers, the minimum step size

is related to the crystal frequency and reference frequency

division ratio.

A sample calculation for an integer-N application is provided in

Figure 5.

synthesizer is in 18-bit mode, the Main Dividend MSB Register

holds the 10 MSBs of the dividend and the Main Dividend LSB

control the main synthesizer’s divide ratio are to be loaded in the

following order:

 Main Divider Register

 Main Dividend LSB Register

 Main Dividend MSB Register (at which point the new divide ratio

takes effect)

In applications where the main synthesizer is in 10-bit mode, the

Main Dividend Register holds the 10 bits of the dividend. The

registers that control the main synthesizer’s divide ratio are to be

loaded in the following order:

 Main Divider Register

 Main Dividend MSB Register (at which point the new divide ratio

takes effect)

For the auxiliary synthesizer, the Auxiliary Dividend Register holds

the 10 bits of the dividend. The registers that control the auxiliary

synthesizer’s divide ratio are to be loaded in the following order:

 Auxiliary Divider Register

 Auxiliary Dividend Register (at which point the new divide ratio

takes effect)

NOTE

: When in integer mode, the new divide ratios take effect

when the Main or Auxiliary Divider Register is loaded.

Direct Digital Modulation

The high fractionality and small step size of the SKY72301-22

allow the VCO to be tuned to practically any frequency in the

VCO’s operating range. This allows direct digital modulation by

programming the different desired frequencies at precise

instants. Typically, the channel frequency is programmed by the

Main Divider and MSB/LSB Dividend registers, and the

instantaneous frequency offset from the carrier is programmed by

the Modulation Data Register.

The Modulation Data Register can be accessed in three ways as

defined in the following subsections.

DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

September 11, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200706C

Case 1: To achieve a desired F

vco_main

frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation

of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (F

div_ref

) is 25 MHz, the crystal

frequency is divided by 2 to obtain a F

div_ref

of 20 MHz. Therefore:

fractional

= F

vco_main

div_ref

= 902.4530

= 45.12265

The value to be programmed in the Main Divider Register is:

reg

= Round[N

fractional

] – 32

= Round[45.12265] – 32

= 45 – 32

= 13 (decimal)

= 000001101 (binary)

With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:

dividend = Round[divider × (N

fractional

– N

reg

– 32)]

= Round[262144 × (45.12265 – 13 – 32)]

= Round[262144 × (0.12265)]

= Round[32151.9616]

= 32152 (decimal)

= 000111110110011000 (binary)

where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the

Main Dividend Register.

Summary:

Main Divider Register = 0 0000 1101

Main Dividend Register, LSB = 1001 1000

Main Dividend Register, MSB = 00 0111 1101

The resulting main VCO frequency is 902.453 MHz

Step size is 76.3 Hz

Note: The frequency step size for this case is 20 MHz divided by 2

, giving 76.3 Hz.

C1414

Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)

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Phase Locked Loops - PLL 1GHz / 500MHz Syn. Phase noise-96dBc/Hz

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