DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
200706C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 11, 2009 9
Table 1. SKY72301-22 Register Map
Address (Hex) Register (Note 1) Length (Bits) Address (Bits)
0 Main Divider Register 12 4
1 Main Dividend MSB Register 12 4
2 Main Dividend LSB Register 12 4
3 Auxiliary Divider Register 12 4
4 Auxiliary Dividend Register 12 4
5 Reference Frequency Dividers Register 12 4
6 Phase Detector/Charge Pumps Control Register 12 4
7 Power Down/Multiplexer Output Select Control Register 12 4
8 Modulation Control Register 12 4
9
—
Modulation Data Register
Modulation Data Register (Note 2) — direct input
12
2 length 12 bits
4
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
When the sum of the dividend and modulation data lie outside this
range, the value of N
integer
must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Modulation Using the SKY72300, SKY72301-22, and SKY72302
Dual Synthesizers/PLLs (document number 101349).
Register Descriptions
Table 1 lists the 10 16-bit registers that are used to program the
SKY72301-22. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power-up,
all registers are reset to 0x000 except registers at address 0x0
and 0x3, which are set to 0x006.
Main Synthesizer Registers
The Main Divider Register contains the integer portion closest to
the desired fractional-N (or the integer-N) value minus 32 for the
main synthesizer. This register, in conjunction with the Main
Dividend MSB/LSB registers (which control the fraction offset
from –0.5 to +0.5), allows selection of a precise frequency. As
shown in Figure 6, the value to be loaded is:
Main Synthesizer Divider Index = Nine-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB/LSB Registers control the fraction part of
the desired fractional-N value and allow an offset of –0.5 to + 0.5
to the main integer selected through the Main Divider Register. As
shown in Figures 7 and 8, values to be loaded are:
Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs
of the 18-bit dividend for the main synthesizer.
The Main Dividend MSB/LSB Register values are 2's complement
format.
NOTE
: When in 10-bit mode, the Main Dividend LSB Register is
not required.
Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest
to the desired fractional-N (or integer-N) value minus 32 for the
auxiliary synthesizer. This register, in conjunction with the
Auxiliary Dividend Register (which controls the fraction offset from
–0.5 to + 0.5) allows selection of a precise frequency. As shown
in Figure 9, the value to be loaded is:
Auxiliary Synthesizer Divider Index = Nine-bit value for the
integer portion of the auxiliary synthesizer dividers. Valid values
for this register are from 6 to 505 (fractional-N) or from 0 to 511
(integer-N).
The Auxiliary Dividend Register controls the fraction part of the
desired fractional-N value and allows an offset of –0.5 to + 0.5 to
the auxiliary integer selected through the Auxiliary Divider
Register. As shown in Figure 10, the value to be loaded is:
Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary
synthesizer dividend.
