XR22801IL32-F Datasheet XR22801IL32-F | P10-P12

XR22801

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USB Device Drivers

Each of the functions in the XR22801 require a USB device driver for operation. Both the I

C and EDGE functions conform

to the HID device class and as such, utilize the embedded HID driver that is native to each Operating System. The Ethernet

function conforms to the CDC device class and as such can utilize an embedded CDC-ECM driver. However, at the time of

this writing, none of the Microsoft OS provide support for CDC-ECM embedded drivers. Both Linux and Mac OS-X platforms

do support CDC-ECM drivers.

The CDC-ECM is a "standard" driver which implements functionality on a specific class of devices. They operate without

any ability to access device specific register sets. In some cases, this can limit the functionality and / or throughput capabil-

ity of the XR22801. Exar provides a custom Ethernet device driver which has been optimized for the best possible data

through-put in Windows and Linux platforms. This custom driver also allows for access to the device register set and thus

full control of the XR22801 device functionality. Refer to 10/100 Ethernet section on page 10 for more details.

The UART function can be used with either a standard CDC-ACM driver or a custom driver. When the CDC-ACM driver is

used, the driver has no ability to read or write the XR22801 device registers. Because of this, the XR22801 device is initial-

ized to the settings in Table3. With a custom driver, all GPIOs default in hardware to inputs but these settings may be mod-

ified by a custom driver.

These default settings can be overridden by programming the OTP.

If a custom driver is used, the CUSTOM_DRIVER_ACTIVE bit should be immediately set to ’1’ by the USB UART driver.

Once the CUSTOM_DRIVER_ACTIVE bit is set, the custom driver can use standard CDC-ACM commands without config-

uring the device to the default register settings used with the CDC-ACM driver. Any changes to the register settings for the

GPIOs and flow control will specifically need to be configured by the driver / application software. Although there is no ability

to read / write registers when using the CDC-ACM driver, basic UART functions, including setting baud rate, character for-

mat and sending line break is supported by the CDC driver. Refer to the 4 CDC_ACM_IF USB Control Commands listed in

Table 4 .

10/100 Ethernet

The Ethernet port is a 10/100 Ethernet MAC and Phy compliant with IEEE 802.3. The Ethernet port supports speed /

duplex auto-negotiation, auto-MDIX, 10 Mbps data auto-polarity, full and half duplex data rates at 10 and 100 Mbps, gener-

ates and validates the 32-bit FCS, and performs unicast and multicast filtering. The XR22801 also performs TCP, UDP and

ICMP checksum offload over IPV4 and IPV6 as well as header checksum offload in IPV4. On chip RAM provides all

required packet buffering.

In Windows OS, using the Exar custom Ethernet driver, the properties dialog, advanced properties can be used to set the

pause frame flow control, speed and duplex, auto-negotiation, checksum offload, and Ethernet remote wakeup settings. By

default, the Ethernet MAC will honor incoming pause frames sent by a peer Ethernet device, but will not generate pause

frames. Auto-MDIX is always enabled.

Ethernet Remote Wakeup

If the XR22801 hub is configured as a self-powered device and has Ethernet remote wakeup enabled, the XR22801 will

request the USB host to resume in response to a magic packet or a link state change on the Ethernet port. When the USB

Table 3: XR22801 Register Defaults With CDC-ACM Driver

Flow Control 0x001 Hardware Flow Control

GPIO_MODE 0x001 RTS / CTS Flow Control

GPIO_DIRECTION 0x008 E3/DTR#/G3 is configured as an output

GPIO_INT_MASK 0x030 E0/RI#/RWK#/G0, E1/CD#/G1 and E2/DSR#/G2 are

interrupt sensitive, i.e. can cause a USB interrupt to

be generated

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host is suspended, the Ethernet Phy remains active and the XR22801 is able to both meet USB suspend mode power

requirements as well as respond to magic packet and link state changes.

The magic packet is an Ethernet packet with specific content, i.e. 6 bytes of 0xFF, followed by 16 repetitions of the target

MAC address (MAC address of the XR22801 device). This content can occur anywhere in the incoming packet payload.

The link state change will wake the USB host if the link is down when the USB host is suspended and then the link goes up,

or if the link is up when the USB host is suspended and then the link goes down.

UART

The UART can be configured via USB control transfers from the USB host. The UART transmitter and receiver sections are

described separately in the following sections. At power-up, the XR22801 will default to 9600 bps, 8 data bits, no parity bit, 1

stop bit, and no flow control. If a standard CDC-ACM driver accesses the XR22801, defaults will change. See Remote

Wakeup section on page 9.

UART transmitter

The transmitter consists of a 1024-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been

received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART

channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data

byte. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if

enabled, and adds the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits

without parity. If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.

UART transmitter - Wide Mode

When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is loaded into the TX

FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is loaded into the TX FIFO is bit-8 of the

9-bit data. The data that is transmitted on the TX pin is as follows: start bit, 9-bit data, stop bit. Use the TX_WIDE_MODE

UART receiver

The receiver consists of a 1024-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the

RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host in response to a bulk-in request.

Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the

data.

UART receiver - Normal mode with 7 or 8-bit data

Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the

data is discarded. Receive data format is shown in Figure 1.

UART receiver - Normal mode with 9-bit data

The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break

status information related to the data is discarded.

Figure 1: UART Normal Receive Data Format with 7 or 8-bit data

byte

7, 8 or 9-bit data

7 6 5 4 3 2 1 0

7 = ‘0’ in 7 bit mode

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UART receiver - Wide mode with 7 or 8-bit data

Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-

ond byte consists of the error bits and break status. Wide mode receive data format is shown in Figure 2. Use the

RX_WIDE_MODE register to enable receive wide mode. Use the RX_WIDE_MODE register to enable receive wide mode.

UART receiver - Wide mode with 9-bit data

Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of the received

data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received / checked. The remainder of

the 2nd byte consists of the framing and overrun error bits and break status.

Figure 2: UART Receive Wide Mode Data Format with 7, 8 or 9-bit data

Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags are historical

flags indicating that an error has occurred since the previous request. Therefore, no conclusion can be drawn as to which

specific byte(s) may have contained an actual error in this manner.

RX FIFO Low Latency

In normal operation all bulk-in transfers will be of maxPacketSize bytes (512 bytes in hi-speed mode and 64 bytes in full-

speed mode) to improve throughput and to minimize host processing. When there are 512 / 64 bytes of data in the RX FIFO,

the XR22801 will acknowledge a bulk-in request from the host and transfer the data packet. If there is less than 512 bytes in

the RX FIFO, the XR22801 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if

there is less than 512 bytes in the RX FIFO and no data has been received for more than 3 character times, the XR22801

will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.

In some cases, especially when the baud rate is low, this increases latency unacceptably. The XR22801 has a low latency

register bit that will cause the XR22801 to immediately transfer any received data in the RX FIFO to the USB host, i.e. it will

not wait for 3 character times. The custom driver may automatically set the RX_CONTROL register to force the XR22801 to

be in the low latency mode, or the user may manually set this bit. With the CDC-ACM driver, the low latency mode is auto-

matically set whenever the baud rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_COD-

ING command.

1st byte

2nd byte

9 bit mode

7 6 5 4 3 2 1 0

x x x x O F B P

1st byte

B = Break

F = Framing Error

O = Overrun Error

2nd byte

7 or 8 bit mode

P = Parity Error (= ‘0’ if not enabled)

7 = ‘0’ in 7 bit mode

x = ‘0’

7 6 5 4 3 2 1 0

x x x x O F B 8B = Break

F = Framing Error

O = Overrun Error

x = ‘0’

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P40

XR22801IL32-F

Mfr. #:

Buy XR22801IL32-F

Manufacturer:

MaxLinear

Description:

I/O Controller Interface IC Hi-Speed USB 10/100 Eth Brdg w 1CH UART

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XR22801IL32-F