© 2014 Exar Corporation
XR22801
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Rev 1A
HID Register Map
Table 9: XR22801 HID Register Map
Address Register Name
Bit 7
(15)
Bit 6
(14)
Bit 5
(13)
Bit 4
(12)
Bit 3
(11)
Bit 2
(10)
Bit 1
(9)
Bit 0
(8)
I
2
C Registers
0x341
I
2
C_SCL_LOW MSB [BITS
15:8]
VALUE (MSB)
I
2
C_SCL_LOW LSB [BITS
7:0]
VALUE (LSB)
0x342
I
2
C_SCL_HIGH MSB [BITS
15:8]
VALUE (MSB)
I
2
C_SCL_HIGH LSB [BITS
7:0]
VALUE (LSB)
EDGE Registers
0x3C0 EDGE_FUNC_SEL E7 E6 E5 E4 E3 E2 E1 E0
0x3C1EDGE_DIR E7E6E5E4E3E2E1E0
0x3C2 EDGE_SET E7 E6 E5 E4 E3 E2 E1 E0
0x3C3 EDGE_CLEAR E7 E6 E5 E4 E3 E2 E1 E0
0x3C4EDGE_STATE E7E6E5E4E3E2E1E0
0x3C5EDGE_TRI_STATE E7E6E5E4E3E2E1E0
0x3C6 EDGE_OPEN_DRAIN E7 E6 E5 E4 E3 E2 E1 E0
0x3C7 EDGE_PULL_UP E7 E6 E5 E4 E3 E2 E1 E0
0x3C8 EDGE_PULL_DOWN E7 E6 E5 E4 E3 E2 E1 E0
0x3C9 EDGE_INTR_MASK E7 E6 E5 E4 E3 E2 E1 E0
0x3CA
EDGE_INTR_POS_
EDGE
E7 E6 E5 E4 E3 E2 E1 E0
0x3CB
EDGE_INTR_NEG_
EDGE
E7 E6 E5 E4 E3 E2 E1 E0
0x3D8
EDGE_PWM0_CTRL MSB
[BITS 15:8]
0000000CMD[2]
EDGE_PWM0_CTRL LSB
[BITS 7:0]
CMD[1:0] EN 0 0 PIN
0x3D9
EDGE_PWM0_HIGH MSB
[BITS 15:8]
0000 VALUE[11:8]
EDGE_PWM0_HIGH LSB
[BITS 7:0]
VALUE [7:0]
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XR22801
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Rev 1A
0x3DA
EDGE_PWM0_LOW MSB
[BITS 15:8]
0000 VALUE[11:8]
EDGE_PWM0_LOW LSB
[BITS 7:0]
VALUE [7:0]
0x3DB
EDGE_PWM1_CTRL MSB
[BITS 15:8]
0000000CMD[2]
EDGE_PWM1_CTRL
LSB [BITS 7:0]
CMD[1:0] EN 0 0 PIN
0x3DC
EDGE_PWM1_HIGH MSB
[BITS 15:8]
0000 VALUE[11:8]
EDGE_PWM1_HIGH LSB
[BITS 7:0]
VALUE [7:0]
0x3DD
EDGE_PWM1_LOW MSB
[BITS 15:8]
0000 VALUE[11:8]
EDGE_PWM1_LOW LSB
[BITS 7:0]
VALUE [7:0]
Table 9: XR22801 HID Register Map
Address Register Name
Bit 7
(15)
Bit 6
(14)
Bit 5
(13)
Bit 4
(12)
Bit 3
(11)
Bit 2
(10)
Bit 1
(9)
Bit 0
(8)
© 2014 Exar Corporation
XR22801
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Rev 1A
HID Register Descriptions
Note that all register reset default values are ’0’ unless otherwise specified. All registers are 16 bits.
I
2
C_SCL_LOW (0x341) - Read/Write
I
2
C_SCL_HIGH (0x342) - Read/Write
EDGE_FUNC_SEL (0x3C0) - Read/Write
EDGE_DIR (0x3C1) - Read/Write
Note that when setting direction of an EDGE IO to output, the EDGE_PULL_UP for that IO pin should also be disabled and
when setting an EDGE IO pin to input, the EDGE_PULL_UP for that IO pin should also be enabled.
Bit Default Description
15:0 0x0144
Value
Specifies the number of periods that SCL will be asserted low by the XR22801 I
2
C master. Note that in clock
stretching, the I
2
C slave may extend the SCL low period to delay the next transaction. For 100 kbps transfer
rate this value must be at least 252 (0x00FC) and the sum of high and low periods must be at least 600
(0x0258). For 400kbps transfer rate this value must be at least 78 (0x004E) and the sum of the high and low
periods must be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns.
Bit Default Description
15:0 0x0114
Value
Specifies the number of periods that SCL will be asserted high by the XR22801 I
2
C master. Note that another
multi-master may assert SCL low before the XR22801 high period is completed. For 100 kbps transfer rate this
value must be at least 240 (0x00F0) and the sum of the high and low periods must be at least 600 (0x0258).
For 400 kbps transfer rate this value must be at least 36 (0x0024) and the sum of the high and low periods must
be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns
Bit Default Description
15:8 0xFF
Reserved
These bits are reserved and should be written as ‘1’.
7:0 0x00
E[7:0]
0: IO is assigned to the UART / GPIO function. IO pin controlled using UART registers.
1: IO is assigned to the EDGE function. IO pin controlled using EDGE registers.
Bit Default Description
15:8 0x00
Reserved
These bits are reserved and should be written as ‘0’.
7:0 0x00
E[7:0]
0: IO pin assigned to EDGE function is configured as an input
1: IO pin assigned to EDGE function is configured as an output.

XR22801IL32-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
I/O Controller Interface IC Hi-Speed USB 10/100 Eth Brdg w 1CH UART
Lifecycle:
New from this manufacturer.
Delivery:
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