© 2014 Exar Corporation
XR22801
14 / 40 exar.com/XR22801
Rev 1A
Automatic RS-485 half duplex control
The Auto RS-485 Half-Duplex Control feature changes the behavior of the E5/RTS#/RS485/G5 pin when enabled by the
GPIO_MODE register bits 2-0. See GPIO_MODE Register Description on page 22. The FLOW_CONTROL register must
also be set appropriately for use in multidrop applications. See FLOW_CONTROL Register Description on page 20. If
enabled, the transmitter automatically asserts the E5/RTS#/RS485/G5 output prior to sending the data. By default, it de-
asserts E5/RTS#/RS485/G5 following the last stop bit of the last character that has been transmitted, but the RS485_DE-
LAY register may be used to delay the deassertion. The polarity of the E5/RTS#/RS485/G5 signal can also be modified
using the GPIO_MODE register bit 3.
Multidrop mode with address matching
The XR22801 device has two address matching modes which are also set by the flow control register using modes 3 and 4.
These modes are intended for a multi-drop network application. In these modes, the XON_CHAR register holds a unicast
address and the XOFF_CHAR holds a multicast address. A unicast address is used by a transmitting master to broadcast
an address to all attached slave devices that is intended for only one slave device. A multicast address is used to broadcast
an address intended for more than one recipient device. Each attached slave device should have a unique unicast address
value stored in the XON_CHAR register, while multiple slaves may have the same multicast adderss stored in the
XOFF_CHAR register. An address match occurs when an address byte (9th bit or parity bit is ’1’) is received that matches
the value stored in either the XON_CHAR or XOFF_CHAR register.
Multidrop mode receiver
If an address match occurs in either flow control mode 3 or 4, the UART Receiver will automatically be enabled and all sub-
sequent data bytes will be loaded into the RX FIFO. The UART Receiver will automatically be disabled when an address
byte is received that does not match the values in the XON_CHAR or XOFF_CHAR register.
Multidrop mode transmitter
In flow control mode 3, the UART transmitter is always enabled, irrespective of the RX address match. In flow control mode
4, the UART transmitter will only be enabled if there is an RX address match.
Programmable Turn-Around Delay
By default, the E5/RTS#/RS485/G5 pin will be de-asserted immediately after the stop bit of the last byte has been shifted.
However, this may not be ideal for systems where the signal needs to propagate over long cables. Therefore, the de-asser-
tion of E5/RTS#/RS485/G5 pin can be delayed from 1 to 15 bit times via the RS485_DELAY register to allow for the data to
reach distant UARTs.
Half-duplex mode
Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In this mode, the UART will ignore any data on the RX input
when the UART is transmitting data.
EDGE - Enhanced Dedicated GPIO Entity
The XR22801 has 8 IO pins that may be assigned to the EDGE. By default, these pins are assigned to the UART function,
either to the UART data and / or flow control pins or to the UART GPIO. Note that UART GPIO and EDGE have separate
register controls. Pins assigned to the UART function cannot be controlled by the EDGE registers and vice versa. To assign
pins to the EDGE, use the EDGE_FUNC_SEL register. See EDGE_FUNC_SEL register description on page 33.
The EDGE controller allows for GPIO signals to be individually set or cleared or to be grouped, such that the all pins in the
group can be simultaneously accessed for reads or writes. Note that on write accesses, output pins will change in 4-bit sub-
groups on core clock (60 MHz) boundaries. For example, if an 8 bit data group is defined and the data value is written from
0x00 to 0xFF, 4 bits would change from ’0’ to ’1’ followed by the next 4 bits one clock cycle (~ 17 ns) later.
EDGE IOs can be configured as inputs or outputs. Outputs can be configured as push-pull or open drain and can be tri-
stated. Inputs can be configured to generate interrupts to the USB host on either negative or postive edge transitions.
