LT3487
10
3487f
Setting the Output Voltages
The LT3487 has an accurate internal feedback resistor
that is trimmed to set the feedback currents to 25µA for
each channel. Only one resistor is needed to set the output
voltage for each channel. The output voltage can be set
according to the following formulas:
R
V
µA
R
V
µA
POS
NEG
1
123
25
2
25
=
=
–.
In order to maintain accuracy, high precision resistors are
preferred (1% is recommended).
Soft-Start
The LT3487 has a single soft-start control for both chan-
nels. The RUN/SS pin is fed by a 1.4μA current source.
The soft-start ramp can be programmed by connecting a
capacitor from the RUN/SS pin to ground. An open-drain
transistor should be used to pull the pin low to shut down
the LT3487. Once the transistor stops sinking the 1.4μA,
the capacitor begins to charge. The chip starts up when
the RUN/SS pin charges to 160mV. The V
CP
node voltage
follows the RUN/SS voltage as it continues to ramp up
to ensure slow start-up on the positive channel. The V
CN
node follows the ramp voltage, down a V
BE
. This ensures
that the negative channel starts up after the positive, but
still has a slow ramping output to avoid large start-up
currents.
Start Sequencing
The LT3487 also has internal sequencing circuitry that
inhibits the negative channel from operating until the
feedback voltage of the boost channel reaches about 1.1V
(87% of the fi nal voltage), ensuring that the sum of the
two outputs is always positive.
There are two ways in which the negative channel may
start up, depending on the size of the soft-start capacitor.
If there is no soft-start capacitor, or a very small capacitor,
then the negative channel will start up when the positive
output reaches 87% of its fi nal value. If a large enough
soft-start capacitor is used, then the RUN/SS voltage will
continue to clamp the negative channel past the point
where the positive channel is in regulation. Figure 3 shows
the start-up sequencing without soft-start, with a small
soft-start capacitor, and a large soft-start capacitor.
Output Disconnect
The output disconnect uses a PNP transistor with circuitry
that varies the base current such that the transistor is
consistently at the edge of saturation, thus yielding the
best compromise between V
CE(SAT)
and low quiescent
current. To remain stable, this circuit requires a bypass
capacitor connected between the V
POS
pin and the CAP pin
or between the V
POS
pin and ground. A ceramic capacitor
with a value of at least 0.1μF is a good choice. Figure 4
shows that the PNP can support load currents of 50mA
with a V
CE
less than 210mV. The disconnect transistor is
current limited to provide a maximum of 155mA in short
circuit.
APPLICATIO S I FOR ATIO
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U
Figure 3a. V
RUN/SS
, V
POS
, V
NEG
,
I
IN
with No Soft-Start Capacitor
Figure 3b. V
RUN/SS
, V
POS
, V
NEG
,
I
IN
with a 10nF Soft-Start Capacitor
Figure 3c. V
RUN
/SS, V
POS
, V
NEG
, I
IN
with a 100nF Soft-Start Capacitor
V
RUN/SS
2V/DIV
I
IN
1A/DIV
V
POS
10V/DIV
V
NEG
10V/DIV
500µs/DIV
3487 F03a
V
RUN/SS
2V/DIV
I
IN
500mA/DIV
V
POS
10V/DIV
V
NEG
10V/DIV
2ms/DIV
3487 F03b
V
RUN/SS
2V/DIV
I
IN
200mA/DIV
V
POS
10V/DIV
V
NEG
10V/DIV
10ms/DIV
3487 F03c
LT3487
11
3487f
Figure 4. V
CE
vs I of Output Disconnect
Choosing a Feedback Node
The positive channel feedback resistor, R1, may be con-
nected to the V
POS
pin or to the CAP pin (see Figure 5).
Regulating the V
POS
pin eliminates the output offset result-
ing from the voltage drop across the output disconnect.
However, in the case of a short-circuit fault at the V
POS
pin, the LT3487 will switch continuously because the FBP
pin is low. While operating in this open-loop condition, the
rising voltage at the CAP pin is limited only by the current
limit of the output disconnect. Given worst-case parameters
this voltage may reach 18V in a Li-Ion application. Care
must be taken in high V
IN
applications when regulating
from the V
POS
pin. When the short-circuit is removed, the
V
POS
pin will bounce up to the voltage on the CAP pin,
potentially exceeding the programmed output voltage until
the capacitor voltages fall back into regulation. While this
is harmless to the LT3487, this should be considered in
the context of the external circuitry if short-circuit events
are expected. Regulating the CAP pin ensures that the
voltage on the V
POS
pin never exceeds the set output volt-
age after a short-circuit event. However, this setup does
not compensate for the voltage drop across the output
disconnect, resulting in an output voltage that is slightly
lower than the voltage set by the feedback resistor. This
voltage drop (V
DISC
) can be accounted for when using
the CAP pin as the feedback node by setting the output
voltage according to the following formula (using V
DISC
from Figure 4):
R
V
µA
DISC
1
123
25
=
+V
POS
–.
V
BAT
The V
BAT
pin is a new innovation in the LT3487 that allows
output disconnect operation in a wide range of applica-
tions. The V
BAT
pin allows the part to stay on until CAP is
less than 1.2V above V
BAT
. This ensures that the positive
bias doesn’t fall before the negative bias discharges. In
some applications it may be useful to power the inductors
from a different source than V
IN
. In this case, connect
V
BAT
to the source powering the inductors to allow proper
operation of the disconnect. For example, in an automotive
system there may already be a buck regulator producing
3.3V from a 12V battery. The LT3487 enables the user
to power V
IN
from the 3.3V rail, but power the V
BAT
pin
APPLICATIO S I FOR ATIO
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Figure 5. Feedback Connection Using the V
POS
and CAP Pins
DISCONNECT CURRENT (mA)
0
0
DISCONNECT SATURATION VOLTAGE (mV)
50
100
150
200
250
300
20 40 60 80
2400 G31
100
SWN
V
IN
CAP
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
FBN
RUN/SS
3487 F05
V
POS
SWN
V
IN
CAP
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
FBN
RUN/SS
V
POS
LT3487
12
3487f
APPLICATIO S I FOR ATIO
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and the inductors directly from the battery for higher ef-
ciency. When the part goes into shutdown, the output
load is isolated from the 12V source as soon as the CAP
node falls to below V
BAT
plus 1.2V (13.2V in this case).
The V
BAT
pin is also useful in a system using a 2V supply
(such as a 2-cell alkaline battery), below the operating
range of the LT3487. A boost converter designed for low
voltage operation can provide 3.3V for the LT3487 V
IN
pin,
while the inductors and V
BAT
can still be powered from the
2V supply. In shutdown, the 3.3V supply will turn off, but
the output disconnect will still decouple the output load
as soon as CAP falls below 3.2V .
Figure 6. Recommended Component Placement
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize effi ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the
SWP and SWN pins have rise and fall times of a few ns.
Minimize the length and area of all traces connected to
the SWP and SWN pins and always use a ground plane
under the switching regulator to minimize interplane
coupling. Recommended component placement is shown
in Figure 6.
V
NEG
V
IN
V
BAT
V
POS
RUN
3487 F06
FBP
CAP
L1 L1
L3
U1
C5
C8
R1
C6
C4
M1
C2 C1
R2
C7

LT3487EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2MHz, Boost /Inverting DC/DC Converter for CCD Bias in DFN
Lifecycle:
New from this manufacturer.
Delivery:
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