LT3487
6
3487f
PI FU CTIO S
UUU
CAP (Pin 1): Disconnect-PNP Emitter and Positive Schottky
Cathode. Acts as an intermediate positive (boost) output.
Connect boost output capacitor to this pin.
SWP (Pin 2): Switch Pin and Schottky Anode for Positive
Channel. Connect boost inductor to this pin.
V
BAT
(Pin 3): Battery Voltage. Connect this pin to the sup-
ply voltage for the boost inductor. The disconnect drive
current is returned to this pin. The disconnect operates
until CAP falls to 1.2V above V
BAT
.
SWN (Pin 4): Switch Pin for Negative (Inverter) Chan-
nel. Connect inverter input inductor and fl ying capacitor
here.
DN (Pin 5): Anode of Internal Schottky for Inverter. Connect
inverter output inductor and fl ying capacitor here.
V
IN
(Pin 6): Input Supply Pin. V
IN
is used to power the
control circuitry of the LT3487. This pin must be locally
bypassed with an X5R or X7R type ceramic capacitor.
FBN (Pin 7): Feedback Pin for Inverter. Connect feedback
resistor R2 from this pin to V
NEG
. Choose R2 according
to:
R
V
µA
NEG
2
25
= –
Pin voltage = 0V when regulated.
RUN/SS (Pin 8): Run/Soft-Start Pin. Connect to an open-
drain transistor. The transistor must sink 1.4µA from
RUN/SS. Pull RUN/SS below 100mV to shut down the chip.
Connect a capacitor from RUN/SS to ground to program
soft-start functionality. The soft-start will slowly bring the
boost channel into regulation and then slowly bring up
the inverter. RUN/SS must be above 1.6V to allow both
channels to reach full current. If soft-start is not required,
this pin can be driven with a logic signal, but the RUN/SS
voltage must remain below V
IN
.
FBP (Pin 9): Feedback Pin for Boost. Connect boost
feedback resistor R1 from FBP to CAP. Choose R1 ac-
cording to:
R
V
µA
POS
1
123
25
=
–.
Pin voltage = 1.23V when regulated.
V
POS
(Pin 10): Output Pin for Boost Channel. V
POS
is
the collector of the output disconnect PNP. Connect the
boost load to V
POS
. Connect capacitor C5 between CAP
and V
POS
for stability.
Exposed Pad (Pin 11): GND. Tie directly to ground plane
through multiple vias under the package for optimum
thermal performance.