LT3487
13
3487f
TYPICAL APPLICATIO
U
V
POS
Load Step Response V
NEG
Load Step Response
+15V and –8V Boost and Inverting CCD Bias
SWN
L2
15µH
L1
10µH
V
IN
CAP
R1
549k
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
L3
15µH
R2 324k
C7 47pF
FBN
RUN/SSRUN/SS
V
NEG
–8V
90mA
C6
100nF
C4
4.7µF
3487 TA02a
C5
100nF
V
POS
15V
45mA
C1
1µF
C2
2.2µF
C3
22µF
V
IN
3V TO 12V
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
V
POS
100mV/DIV
AC-COUPLED
45mA
I
POS
15mA
100µs/DIV
3487 TA02b
V
IN
= 3.6V
V
NEG
20mV/DIV
AC-COUPLED
–50mA
I
NEG
–90mA
100µs/DIV
3487 TA02c
V
IN
= 3.6V
The positive channel’s response is stable, but slightly
underdamped. A phase lead capacitor (C8) can be added
to provide more ideal phase margin.
V
POS
Load Step Response (with Phase Lead Capacitor)
V
POS
100mV/DIV
AC-COUPLED
45mA
I
POS
15mA
100µs/DIV
3487 TA02d
V
IN
= 3.6V
CAP
R2
549k
C8
10pF
FBP
3487 TA02e
LT3487
14
3487f
TYPICAL APPLICATIO S
U
+15V and –8V Low V
IN
CCD Bias
SWN
L2
15µH
L1
10µH
V
IN
CAP
R1
549k
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
L3
15µH
R2 324k
C7 33pF
FBN
RUN/SSRUN/SS
V
NEG
–8V
80mA
C6
100nF
C4
4.7µF
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN EMK212BJ225MD-TR
C3: TAIYO YUDEN TMK325BJ226MM
C4: TAIYO YUDEN TMK316BJ475ML-TR
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
3487 TA03
C5
100nF
C8
15pF
V
POS
15V
40mA
C1
1µF
C2
2.2µF
C3
22µF
V
IN
2.7V TO 5V
+15V and –8V Boost and Charge Pump CCD Bias
SWN
L2
15µH
L1
10µH
V
IN
CAP
R1
549k
FBP
V
POS
V
BAT
LT3487
GND
SWP
DN
D1
R2 324k
C7 20pF
FBN
RUN/SSRUN/SS
V
NEG
–8V
90mA
C6
100nF
C4
4.7µF
C1: TAIYO YUDEN EMK212BJ105MG
C2: TAIYO YUDEN TMK212BJ225MG
C3: TAIYO YUDEN EMK316BJ106ML
C4: TAIYO YUDEN TMK316BJ475ML-TR
D1: PHILIPS PMEG2010AEB
L1: TOKO DB318C-A997AS-100M
L2, L3: SUMIDA CDRH2D18/HP-150NC
3487 TA04
C5
100nF
V
POS
15V
45mA
C1
1µF
C2
2.2µF
C3
10µF
V
IN
3V TO 12V
LT3487
15
3487f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PACKAGE DESCRIPTIO
U

LT3487EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2MHz, Boost /Inverting DC/DC Converter for CCD Bias in DFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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