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8P73S674NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15
DATA SHEET
1.8V LVPECL Clock Divider 8P73S674
8P73S674 REVISION 1 12/17/14 1 ©2014 Integrated Device Technology, Inc.
General Description
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.
The device has been designed for clock signal division and fanout in
wireless base station (radio and base band), high-end computing and
telecommunication equipment. The device is optimized to deliver
excellent phase noise performance. The 8P73S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew 1.8V LVPECL outputs are available for and support clock
output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL
outputs are terminated 50
to GND. Outputs can be disabled to save
power consumption if not used. The device is packaged in a lead-free
(RoHS 6) 20-lead VFQFN package. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
• Clock signal division and distribution
• SiGe technology for high-frequency and fast signal rise/fall times
• Four low-skew LVPECL clock outputs
• Supports frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum Output frequency: 1GHz
• Output skew: 100ps (maximum)
• LVPECL output rise/fall time (20% - 80%): 220ps (maximum)
• 1.8V core and output supply mode
• Supports 1.8V I/O LVCMOS logic levels for all control pins
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) 20-lead VFQFN packaging
Block Diagram
÷N
IN
nIN
VT
N[1:0]
nOEA
nOEB
2x 50
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
8P73S674
VCC
Q2
nQ2
Q1
nQ1
GND
N1
nOEB
nQ3
Q3
6 7 8910
20
19 18 17
16
GND
nOEA
VCC
Q0
nQ0
N0
IN
VT
NC
nIN
2
3
4
5
115
14
13
12
11
20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package
Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
8P73S674 DATA SHEET
1.8V LVPECL CLOCK DIVIDER 2 REVISION 1 12/17/14
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number Name Type Description
1 nIN Input — Clock signal inverting differential input. Internal termination 50 to VT.
2 NC Unused — Not connected.
3 VT — — Leave open if IN, nIN is used with LVDS signals.
4 IN Input — Clock signal non-inverting differential input. Internal termination 50 to VT.
5 N0 Input Pulldown Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
6 GND Power — Power supply ground.
7 N1 Input Pulldown Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
8 nOEB Input Pulldown
Output enable control for the Q1, Q2 and Q3 outputs.
1.8V LVCMOS/LVTTL interface levels.
9 nQ3 Output —
Differential clock output 3. 1.8V LVPECL output levels.
10 Q3 Output —
11 V
CC
Power — Supply voltage for the clock outputs.
12 Q2 Output —
Differential clock output 2. 1.8V LVPECL output levels.
13 nQ2 Output —
14 Q1 Output —
Differential clock output 1. 1.8V LVPECL output levels.
15 nQ1 Output —
16 V
CC
Power — Supply voltage for the clock outputs.
17 Q0 Output —
Differential clock output 0. 1.8V LVPECL output levels.
18 nQ0 Output —
19 nOEA Input Pulldown
Output enable control for the Q0 output.
1.8V LVCMOS/LVTTL interface levels.
20 GND Power — Power supply ground.
EPAD GND_EP Power —
Exposed package pad negative supply voltage (GND).
Return current path for the Q0, Q1, Q2 and Q3 outputs.
Table 2. Pin Characteristics
Symbol Parameter
REVISION 1 12/17/14 3 1.8V LVPECL CLOCK DIVIDER
8P73S674 DATA SHEET
Truth Tables
0 (default) 0 (default) ÷1
0 1 ÷2
1 0 ÷4
1 1 ÷8
Table 3B. nOEA Output Enable
Input Output
nOEA Q0
0 (default) Output is enabled
1 Output is disabled in logic low state
Table 3C. nOEB Output Enable
Input Output
nOEB Q1, Q2, Q3
0 (default) Outputs are enabled
1 Outputs are disabled in logic low state
Table 3A. N Clock Divider
Input
Divider ValueN1 N0
P1-P3P4-P6P7-P9P10-P12P13-P15

8P73S674NLGI

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Clock Drivers & Distribution Differential-to-1.8 LVPECL Clock Divide
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