8P73S674 DATA SHEET
1.8V LVPECL CLOCK DIVIDER 10 REVISION 1 12/17/14
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 3.
Figure 3. LVPECL Driver Circuit and Termination
To calculate power dissipation due to loading, use the following equations which assume a 50 load.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.75V
(V
CC_MAX
– V
OH_MAX
) = 0.75V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.5V
(V
CC_MAX
– V
OL_MAX
) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
)/R
L
] * (V
CC_MAX
– V
OH_MAX
)
= [(V
CC_MAX
– 0.75)/R
L
] * (V
CC_MAX
– V
OH_MAX
)
= [(1.95V – 0.75V)/50] * 0.75V = 18mW
Pd_L = [(V
OL_MAX
)/R
L
] * (V
CC_MAX
– V
OL_MAX
)
= [(V
CC_MAX
– 1.5v)/R
L
] * (V
CC_MAX
– V
OL_MAX
)
= [(1.95V – 1.5V)/50] * 1.5V = 13.5mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.5mW
