MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
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Note 1: Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±4.096V input range.
Note 2: External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale. V
DD
= 4.75V to 5.25V.
Note 9: External acquisition timing: starts at rising edge of WR
with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
Note 12: t
DO
and t
DO1
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13: t
TR
is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
(Note 13) ns
70
CONDITIONS
t
TR
RD High to Output Disable
ns120t
INT1
RD Low to INT High Delay
ns80t
CS
CS Pulse Width
UNITSMIN TYP MAXSYMBOLPARAMETER
ns80t
WR
WR Pulse Width
ns0t
CSWS
ns0t
CSWH
CS to WR Hold Time
CS to WR Setup Time
ns0t
CSRS
ns0t
CSRH
CS to RD Hold Time
CS to RD Setup Time
ns100t
CWS
ns50t
CWH
CLK to WR Hold Time
CLK to WR Setup Time
ns60t
DS
ns0t
DH
Data Valid to WR Hold
Data Valid to WR Setup
Figure 2, C
L
= 100pF (Note 12)
Figure 2, C
L
= 100pF (Note 12)
ns120t
DO
ns120t
DO1
HBEN High or HBEN Low to
Output Valid
RD Low to Output Data Valid
