MAX199BCWI Datasheet MAX199BCAI+, MAX199BEWI+T, MAX199BCWI+T | P7-P9

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_______________________________________________________________________________________ 7

______________________________________________________________Pin Description

Digital GroundDGND28

+5V Supply. Bypass with 0.1µF capacitor to AGND.V

INT goes low when conversion is complete and output data is ready.INT24

Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.

Connect to V

when using an external reference at the REF pin.

REFADJ25

Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a

4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal

buffer by pulling REFADJ to V

REF26

Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).D2/D1012

Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).D1/D913

Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.D0/D814

Analog GroundAGND15

Analog Input ChannelsCH0–CH716–23

Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;

when low, the 8 LSBs are available on the bus.

HBEN5

Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.SHDN6

Three-State Digital I/OD7–D47–10

Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).D3/D1111

When CS is low, a falling edge on RD will enable a read operation on the data bus.RD4

When CS is low, in the internal acquisition mode, a rising edge on WRlatches in configuration data and starts an

acquisition plus a conversion cycle. When CSis low, in the external acquisition mode, the first rising edge on

WR starts an acquisition and a second rising edge on WRends acquisition and starts a conversion cycle.

WR3

Chip Select, active low.CS2

Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,

place a capacitor (C

CLK

) from this pin to ground to set the internal clock frequency; f

CLK

= 1.56MHz typical

with C

CLK

= 100pF.

CLK1

FUNCTIONNAME

100k

510k

24k

REFADJ

+5V

0.01µF

MAX199

Figure 1. Reference-Adjust Circuit

OUT

+5V

a) High-Z to V

and V

to V

b) High-Z to V

and V

to V

LOAD

Figure 2. Load Circuits for Enable Time

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

8 _______________________________________________________________________________________

_______________Detailed Description

Converter Operation

The MAX199, a multi-range, fault-tolerant ADC, uses

successive approximation and internal input track/hold

(T/H) circuitry to convert an analog signal to a 12-bit

digital output. The parallel-output format provides easy

interface to microprocessors (µPs). Figure 3 shows the

MAX199 in its simplest operational configuration.

Analog-Input Track/Hold

In the internal acquisition control mode (control bit D5

set to 0), the T/H enters its tracking mode on WR’s ris-

ing edge, and enters its hold mode when the internally

timed (6 clock cycles) acquisition interval ends. In bipo-

lar mode, a low-impedance input source, which settles

in less than 1.5µs, is required to maintain conversion

accuracy at the maximum conversion rate.

When configured for unipolar mode, the input does not

need to be driven from a low-impedance source. The

acquisition time (t

) is a function of the source output

resistance (R

), the channel input resistance (R

), and

the T/H capacitance.

Acquisition time is calculated by:

For 0V to V

REF

: t

= 9 x (R

+ R

) x 16pF

For 0V to V

REF/2

: t

= 9 x (R

+ R

) x 32pF

where R

= 7kΩ, and t

is never less than 2µs (0V to

REF

range) or 3µs (0V to V

REF/2

range).

In the external acquisition control mode (D5 = 1), the

T/H enters its tracking mode on the first WR rising edge

and enters its hold mode when it detects the second WR

rising edge with D5 = 0. See the

External Acquisition

section.

Input Bandwidth

The ADC’s input tracking circuitry has a 5MHz small-

signal bandwidth. When using the internal acquisition

mode with an external clock frequency of 2MHz, a

100ksps throughput rate can be achieved. It is possible

to digitize high-speed transient events and measure

periodic signals with bandwidths exceeding the ADC’s

sampling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended (MAX274/MAX275 continuous-time filters).

Input Range and Protection

Figure 4 shows the equivalent input circuit. The MAX199

can be programmed for input ranges of ±V

REF

, ±V

REF/2

0V to V

REF

, or 0V to V

REF/2

by setting the appropriate

control bits (D3, D4) in the control byte (see Tables 1 and

2). When an external reference is applied at REFADJ, the

voltage at REF is given by V

REF

= 1.6384 x V

REFADJ

(2.4V

< V

REF

< 4.18V).

DGND

REF

REFADJ

INT

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

AGND

4.7µF

0.1µF

+5V

+4.096V

OUTPUT STATUS

µP

CONTROL

INPUTS

CLK

HBEN

SHDN

D3/D11

D2/D10

D1/D9

D0/D8

100pF

µP DATA BUS

ANALOG

INPUTS

MAX199

Figure 3. Operational Diagram

5.12k

CH_

BIPOLAR

UNIPOLAR

VOLTAGE

REFERENCE

T/H

OUT

HOLDTRACK

TRACKHOLD

OFF

HOLD

S1 = BIPOLAR/UNIPOLAR SWITCH

S2 = INPUT MUX SWITCH

S3, S4 = T/H SWITCH

Figure 4. Equivalent Input Circuit

The input channels are overvoltage protected to

±16.5V. This protection is active even if the device is in

power-down mode.

Even with V

= 0V, the input resistive network provides

current-limiting that adequately protects the device.

Digital Interface

Input data (control byte) and output data are multiplexed

on a three-state parallel interface. This parallel I/O can

easily be interfaced with a µP. CS, WR, and RD control

the write and read operations. CS is the standard chip-

select signal, which enables a µP to address the MAX199

as an I/O port. When high, it disables the WR and RD

inputs and forces the interface into a high-Z state.

Input Format

The control byte is latched into the device, on pins

D7–D0, during a write cycle. Table 1 shows the control-

byte format.

Output Data Format

The output data format is binary in unipolar mode and

twos-complement binary in bipolar mode. When read-

ing the output data, CS and RD must be low. When

HBEN is low, the lower eight bits are read. When HBEN

is high, the upper four MSBs are available and the out-

put data bits D4–D7 are either set low (in unipolar

mode) or set to the value of the MSB (in bipolar mode)

(Table 5).

MAX199

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

_______________________________________________________________________________________ 9

Table 1. Control-Byte Format

D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)

PD1 PD0 ACQMOD RNG BIP A2 A1 A0

Table 3. Clock and Power-Down Selection

PD1 PD0 DEVICE MODE

0 0 Normal Operation / External Clock Mode

0 1 Normal Operation / Internal Clock Mode

1 0

Standby Power-Down (STBYPD); clock mode

is unaffected

1 1

Full Power-Down (FULLPD); clock mode is

unaffected

Table 2. Range and Polarity Selection

BIP RNG INPUT RANGE (V)

0 0 0 to V

REF/2

0 1 0 to V

REF

1 0 ±V

REF/2

1 1 ±V

REF

Table 4. Channel Selection

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0 0 0

∗

0 0 1

∗

0 1 0

∗

0 1 1

∗

1 0 0

∗

1 0 1

∗

1 1 0

∗

1 1 1

∗

BIT NAME DESCRIPTION

7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 3).

5 ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition

4 RNG Selects the full-scale voltage magnitude at the input (Table 2).

3 BIP Selects unipolar or bipolar conversion mode (Table 2).

2, 1, 0 A2, A1, A0 These are address bits for the input mux to select the “on” channel (Table 4).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX199BCWI

Mfr. #:

Buy MAX199BCWI

Manufacturer:

Maxim Integrated

Description:

IC DAS 12BIT 100KSPS BUS 28-SOIC

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MAX199BCWI

MAX199BCWI

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