MAX791
Watchdog-Pulse Output
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog-timeout period, WDPO will pulse low
for 1ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the
flip-flop’s Q output remains high as WDO goes low
(Figure 5). If the watchdog timer is not reset by a transi-
tion at WDI, WDO remains low and WDPO clocks a
logic low to the Q output, causing the MAX791 to latch
in reset. If the watchdog timer is reset by a transition at
WDI, WDO goes high and the flip-flop’s Q output
remains high. Thus, a system shutdown is only caused
by two successive watchdog faults.
The internal pull-up resistors associated with WDO and
WDPO connect to V
OUT
. Therefore, do not connect
these outputs directly to CMOS logic that is powered
from V
CC
since, in the absence of V
CC
(i.e., battery
mode), excessive current will flow from WDO or
WDPO through the protection diode(s) of the CMOS-
logic inputs to ground.
Selecting an Alternative Watchdog-
Timeout Period
SWT input controls the watchdog-timeout period.
Connecting SWT to V
OUT
selects the internal 1.6s watch-
dog-timeout period. Select an alternative timeout period
by connecting a capacitor between SWT and GND. Do
not leave SWT floating, and do not connect it to ground.
The following formula determines the watchdog-timeout
period:
Watchdog-timeout period = 2.1 x (capacitor value
in nF) ms
This formula is valid for capacitance values between
4.7nF and 100nF (see the Watchdog Timeout vs.
Timing Capacitor graph in the Typical Operating
Characteristics). SWT is internally connected to a
±100nA (typ) current source, which charges and dis-
charges the timing capacitor to create the oscillator fre-
quency that sets the watchdog-timeout period (see
Connecting a Timing Capacitor to SWT section).
Chip-Enable Signal Gating
The MAX791 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX791 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
CE OUT (Figure 1).
The 10ns max CE propagation from CE IN to CE OUT
Microprocessor Supervisory Circuit
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