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MAX791ESE+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MAX791
Microprocessor Supervisory Circuit
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 VBATT
2V
OUT
Output Supply Voltage. V
OUT
connects to V
CC
when V
CC
is greater than VBATT and V
CC
is above the reset
threshold. When V
CC
falls below VBATT and V
CC
is below the reset threshold, V
OUT
connects to VBATT.
Connect a 0.1µF capacitor from V
OUT
to GND.
3V
CC
Input Supply Voltage—+5V input
4 GND
5 BATT ON
6
–
P
—
F
—
O
–
7 PFI
8 SWT
9
–
M
—
R
–
10
–
L
—
O
—
W
— —
L
—
I
—
N
—
E
–
11 WDI
12
–
C
—
E
–
OUT
Chip-Enable Output.
–
C
—
E
–
OUT goes low only when
––
C
—
E
–
IN is low and V
CC
is above the reset threshold. If
–
C
—
E
–
IN is
low when reset is asserted,
–
C
—
E
–
OUT will stay low for 15µs or until
–
C
—
E
–
IN goes high, whichever occurs first.
13
––
C
—
E
–
IN
Backup-Battery Input. Connect to external battery or capacitor and charging circuit.
Ground. 0V reference for all signals.
Battery-On Output. Goes high when V
OUT
switches to VBATT. Goes low when V
OUT
switches to V
CC
. Connect
the base of a PNP through a current-limiting resistor to BATT ON for V
OUT
current requirements greater than
250mA.
Power-Fail Output. This is the output of the power-fail comparator.
–
P
—
F
—
O
–
goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V,
–
P
—
F
—
O
–
goes low. Connect PFI to GND or V
OUT
when not used.
Set Watchdog-Timeout Input. Connect this input to V
OUT
to select the default 1.6s watchdog-timeout period.
Connect a capacitor between this input and GND to select another watchdog-timeout period. Watchdog-timeout
period = 2.1 x (capacitor value in nF) ms.
16
–
W
—
D
—
P
—
O
–
15
–
R
—
E
—
S
—
E
—
T
–
14
–
W
—
D
—
O
–
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate out-
put.
–
R
—
E
—
S
—
E
—
T
–
remains low as long as
–
M
—
R
–
is held low and for 200ms after
–
M
—
R
–
returns high.
–
L
—
O
—
W
— —
L
—
I
—
N
—
E
–
Output goes low when V
CC
falls to 150mV above the reset threshold. The output can be used to gen-
erate an NMI if the unregulated supply is inaccessible.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
out period,
–
W
—
D
—
O
–
goes low.
–
W
—
D
—
O
–
remains low until the next transition at WDI. Leaving WDI unconnected disables
the watchdog function. WDI connects to an internal voltage-divider between V
OUT
and GND, which sets it to mid-
supply when left unconnected.
Chip-Enable Input. The input to chip-enable gating circuit. Connect to GND or V
OUT
if not used.
Watchdog Output.
–
W
—
D
—
O
–
goes low if WDI remains either high or low longer than the watchdog-timeout period.
–
W
—
D
—
O
–
returns high on the next transition at WDI.
–
W
—
D
—
O
–
remains high if WDI is unconnected.
–
W
—
D
—
O
–
is also high
when
–
R
—
E
—
S
—
E
—
T
–
is asserted.
–
R
—
E
—
S
—
E
—
T
–
Output goes low whenever V
CC
falls below the reset threshold.
–
R
—
E
—
S
—
E
—
T
–
will remain low for typically 200ms
after V
CC
crosses the reset threshold on power-up.
Watchdog-Pulse Output. Upon the absence of a transition at WDI,
–
W
—
D
—
P
—
O
–
will pulse low for a minimum of 1ms.
–
W
—
D
—
P
—
O
–
precedes
––
W
—
D
—
O
–
by 70ns.
_______________Detailed Description
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator or test technician to initiate a
reset. The Manual Reset Input (MR) can be connected
directly to a switch, without an external pull-up resistor
or debouncing network. It connects to a 1.25V com-
parator, and has a pull-up to V
OUT
as shown in Figure
1. The propagation delay from asserting MR to RESET
asserted is 4µs typ. Pulsing MR low for a minimum of
15µs resets all the internal counters, sets the Watchdog
Output (WDO) and Watchdog-Pulse Output (WDPO)
high, and sets the Set Watchdog-Timeout (SWT) input
to V
OUT
- 0.6V, if it is not already connected to V
OUT
(for internal timeouts). It also disables the chip-enable
function, setting the Chip-Enable Output (CE OUT) to a
high state. The RESET output remains active as long as
MR is held low, and the reset-timeout period begins
after MR returns high (Figure 2).
Use this input as either a digital-logic input or a second
low-line comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
MAX791
Microprocessor Supervisory Circuit
8 _______________________________________________________________________________________
MAX791
CHIP-ENABLE
OUTPUT
CONTROL
V
CC
3
1
13
9
8
11
7
VBATT
CE IN
MR
SWT
WDI
PFI
RESET
GENERATION
TIMEBASE FOR
RESET AND
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
V
OUT
1.25V
GND
4
4.65V
150mV
10
LOWLINE
5
2
12
15
16
14
PFO
WDO
WDPO
RESET
CE OUT
6
V
OUT
BATT ON
Figure 1. MAX791 Block Diagram
MR
RESET
CE IN
0V
7.5µs TYP
15µs TYP
25µs MIN
CE OUT
Figure 2. Manual-Reset Timing Diagram
MAX791
*
*
OTHER
RESET
SOURCES
MANUAL RESET
MR
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" Connections Allow Multiple Reset Sources
to Connect to MR
RESET Output
The MAX791’s RESET output ensures that the µP pow-
ers up in a known state, and prevents code-execution
errors during power-down or brownout conditions.
The RESET output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
When deasserted, RESET sources 1.6mA at typically
V
OUT
- 0.5V. When no backup battery is used, RESET
output is guaranteed to be valid down to V
CC
= 1V, and
an external 10kΩ pull-down resistor on RESET ensures
that RESET will be valid with V
CC
down to GND (Figure
4). As V
CC
goes below 1V, the gate drive to the RESET
output switch reduces accordingly, increasing the
r
DS(ON)
and the saturation voltage. The 10kΩ pull-down
resistor ensures the parallel combination of switch plus
resistor is around 10kΩ and the output saturation volt-
age is below 0.4V while sinking 40µA. When using a
10kΩ external pull-down resistor, the high state for the
RESET output with V
CC
= 4.75V is 4.5V typ. For battery
voltages ≥ 2V connected to VBATT, RESET remains
valid for V
CC
from 0V to 5.5V.
RESET will be asserted during the following conditions:
•V
CC
< 4.65V (typ).
•MR< 1.25V (typ).
• RESET remains asserted for 200ms (typ) after V
CC
rises above 4.65V or after MR has exceeded
1.25V.
The MAX791 battery-switchover comparator does not
affect RESET assertion. However, RESET is asserted in
battery-backup mode since V
CC
must be below the
reset threshold to enter this mode.
Watchdog Function
The watchdog monitors µP activity via the Watchdog
Input (WDI). If the µP becomes inactive, WDO and
WDPO are asserted. To use the watchdog function,
connect WDI to a bus line or µP I/O line. If WDI remains
high or low for longer than the watchdog timeout period
(1.6s nominal), WDPO and WDO are asserted, indicat-
ing a software fault condition (see Watchdog Output
and Watchdog-Pulse Output sections).
Watchdog Input
A change of state (high to low, low to high, or a mini-
mum 100ns pulse) at WDI during the watchdog period
resets the watchdog timer. The watchdog default time-
out is 1.6s. Select alternative timeout periods by con-
necting an external capacitor from SWT to GND (see
Selecting an Alternative Watchdog Timeout Period sec-
tion).
To disable the watchdog function, leave WDI floating.
An internal resistor network (100kΩ equivalent imped-
ance at WDI) biases WDI to approximately 1.6V.
Internal comparators detect this level and disable the
watchdog timer. When V
CC
is below the reset thresh-
old, the watchdog function is disabled and WDI is dis-
connected from its internal resistor network, thus
becoming high impedance.
Watchdog Output
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. The watch-
dog function is disabled and WDO is a logic high when
V
CC
is below the reset threshold, battery-backup mode
is enabled, or WDI is an open circuit. In watchdog
mode, if no transition occurs at WDI during the watch-
dog-timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next
transition at WDI (Figure 5). A flip-flop can force the
system into a hardware shutdown if there are two suc-
cessive watchdog faults (Figure 6). WDO has a 2 x TTL
output characteristic.
MAX791
Microprocessor Supervisory Circuit
_______________________________________________________________________________________ 9
MAX791
RESET
10k
TO µP RESET
15
Figure 4. Adding an External Pull-Down Resistor Ensures
–
R
—
E
—
S
—
E
—
T
–
is Valid with V
CC
Down to GND
WDPO
WDI
70ns
1.6s
100ns MIN
WDO
Figure 5. WDI,
–
W
—
D
—
O
–
, and
–
W
—
D
—
P
—
O
–
Timing Diagram (V
CC
Mode)
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MAX791ESE+

Mfr. #:
Buy MAX791ESE+
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits MPU Supervisor
Lifecycle:
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