Battery On Output
The Battery On (BATT ON) output indicates the status
of the internal V
CC
/battery-switchover comparator,
which controls the internal V
CC
and VBATT switches.
For V
CC
greater than VBATT (ignoring the small hys-
teresis effect), BATT ON typically sinks 3.2mA at 0.1V
saturation voltage. In battery-backup mode, this termi-
nal sources approximately 10µA from V
OUT
. Use BATT
ON to indicate battery-switchover status or to supply
base drive to an external pass transistor for higher-cur-
rent applications (see Typical Operating Circuit).
Input Supply Voltage
The Input Supply Voltage (V
CC
) should be a regulated
+5V. V
CC
connects to V
OUT
via a parallel diode and a
large PMOS switch. The switch carries the entire cur-
rent load for currents less than 250mA. The parallel
diode carries any current in excess of 250mA. Both the
switch and the diode have impedances less than 1
each (Figure 10). The maximum continuous current is
250mA, but power-on transients may reach a maximum
of 1A.
Backup-Battery Input
The Backup-Battery Input (VBATT) is similar to V
CC
,
except the PMOS switch and parallel diode are much
smaller. Accordingly, the on-resistances of the diode
and the switch are each approximately 10.
Continuous current should be limited to 25mA and peak
currents (only during power-up) limited to 250mA. The
reverse leakage of this input is less than 1µA over tem-
perature and supply voltage.
Output Supply Voltage
The Output Supply Voltage (V
OUT
) is internally connect-
ed to the substrate of the IC and supplies all the current
to the external system and internal circuitry. All open-
circuit outputs will, for example, assume the V
OUT
volt-
age in their high states rather than the V
CC
voltage. At
the maximum source current of 250mA, V
OUT
will typi-
cally be 200mV below V
CC
. Decouple this terminal with
a 0.1µF capacitor.
Low-Battery Monitor
The MAX791 low-battery voltage function monitors
VBATT. Low-battery detection of 2.0V ±0.15V is moni-
tored only during the reset-timeout period (200ms) that
occurs either after a normal power-up sequence or
after the MR reset input has been returned to its high
state. If the battery voltage is below 2.0V, the second
CE pulse is inhibited after reset timeout. If the battery
voltage is above 2.0V, all CE pulses are allowed
through the CE gate after the reset timeout period. To
use this function, after the 200ms reset delay, write 00
(HEX) to a location using the first CE pulse, and write
FF (HEX) to the same location using the second CE
pulse following RESET going inactive on power-up. The
contents of the memory then indicates a good battery
(FF) or a low battery (00) (Figure 11).
MAX791
Microprocessor Supervisory Circuit
______________________________________________________________________________________ 13
200ms TYP
RESET
THRESHOLD
V
CC
RESET
CE IN
CE OUT
SECOND CE PULSE ABSENT WHEN VBATT < 2V
Figure 11. Backup-Battery Monitor Timing Diagram
MAX791
VBATT
V
CC
1
3
2
0.1µF
V
OUT
Figure 10. V
CC
and VBATT-to-V
OUT
Switch
MAX791
Applications Information
The MAX791 is not short-circuit protected. Shorting
V
OUT
to ground, other than power-up transients such
as charging a decoupling capacitor, destroys the
device.
All open-circuit outputs swing between V
OUT
and GND
rather than V
CC
and GND.
If long leads connect to the chip inputs, ensure that
these lines are free from ringing and other conditions
that would forward bias the chip’s protection diodes.
There are three distinct modes of operation:
1) Normal operating mode with all circuitry powered
up. Typical supply current from V
CC
is 60µA, while
only leakage currents flow from the battery.
2) Battery-backup mode where V
CC
is typically within
0.7V below VBATT. All circuitry is powered up and
the supply current from the battery is typically less
than 60µA.
3) Battery-backup mode where V
CC
is less than
VBATT by at least 0.7V. VBATT supply current is
less than 1µA max.
Using SuperCaps or MaxCaps
with the MAX791
VBATT has the same operating voltage range as V
CC
,
and the battery-switchover threshold voltages are typi-
cally ±30mV centered at VBATT, allowing use of a
SuperCap and a simple charging circuit as a backup
source (Figure 12).
If V
CC
is above the reset threshold and VBATT is 0.5V
above V
CC
, current flows to V
OUT
and V
CC
from VBATT
until the voltage at VBATT is less than 0.5V above V
CC
.
For example, with a SuperCap connected to VBATT
and through a diode to V
CC
, if V
CC
quickly changes
from 5.4V to 4.9V, the capacitor discharges through
V
OUT
and V
CC
until VBATT reaches 5.3V typ. Leakage
current through the SuperCap charging diode and
MAX791 internal power diode eventually discharges the
SuperCap to V
CC
. Also, if V
CC
and VBATT start from
0.5V above the reset threshold and power is lost at
V
CC
, the SuperCap on VBATT discharges through V
CC
until VBATT reaches the reset threshold; the MAX791
then switches to battery-backup mode and the current
through V
CC
goes to zero (Figure 10).
Using Separate Power Supplies
for VBATT and V
CC
If using separate power supplies for V
CC
and VBATT,
VBATT must be less than 0.3V above V
CC
when V
CC
is
above the reset threshold. As described in the previous
section, if VBATT exceeds this limit and power is lost at
V
CC
, current flows continuously from VBATT to V
CC
via
the VBATT-to-V
OUT
diode and the V
OUT
-to-V
CC
switch
until the circuit is broken (Figure 10).
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows
the MAX791 CE loop to be bypassed. To do this, con-
nect CE IN to ground, pull up CE OUT to V
OUT
, and
connect CE OUT to the CE input of each memory
device (Figure 13). The CE input of each part then con-
nects directly to the chip-select logic, which does not
have to be gated by the MAX791.
Adding Hysteresis to the
Power-Fail Comparator
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of PFO when
VIN is near the power-fail comparator trip point. Figure
14 shows how to add hysteresis to the power-fail com-
parator. Select the ratio of R1 and R2 so that PFI sees
1.25V when VIN falls to the desired trip point (V
TRIP
).
Resistor R3 adds hysteresis. It will typically be an order
of magnitude greater than R1 or R2. The current
through R1 and R2 should be at least 1µA to ensure
that the 25nA (max) PFI input current does not shift the
trip point. R3 should be larger than 10k to prevent it
from loading down the PFO pin. Capacitor C1 adds
additional noise rejection.
Microprocessor Supervisory Circuit
14 ______________________________________________________________________________________
MAX791
1
0.47F
1N4148
+5V
2
3
V
CC
GND
VBATT
4
V
OUT
Figure 12. SuperCap or MaxCap on VBATT
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 15’s circuit. When
the negative supply is valid, PFO is low. When the neg-
ative supply voltage drops, PFO goes high. This cir-
cuit’s accuracy is affected by the PFI threshold toler-
ance, the V
CC
voltage, and resistors R1 and R2.
Backup-Battery Replacement
The backup battery may be disconnected while V
CC
is
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
Negative-Going V
CC
Transients
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going V
CC
transients (glitches). It is usually undesirable to reset
the µP when V
CC
experiences only small glitches.
Figure 16 shows maximum transient duration vs. reset
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going V
CC
pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset com-
parator overdrive). The graph shows the maximum
pulse width that a negative-going V
CC
transient may
typically have without causing a reset pulse to be
issued. As the amplitude of the transient increases (i.e.,
goes farther below the reset threshold), the maximum
allowable pulse width decreases. Typically, a V
CC
tran-
sient that goes 100mV below the reset threshold and
lasts for 40µs or less will not cause a reset pulse to be
issued.
A 100nF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
Connecting a Timing Capacitor to SWT
SWT is internally connected to a ±100nA current
source. When a capacitor is connected from SWT to
ground (to select an alternative watchdog-timeout peri-
od), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
watchdog-timeout period. To prevent timing errors or
oscillator start-up problems, minimize external current
leakage sources at this pin, and locate the capacitor as
MAX791
Microprocessor Supervisory Circuit
______________________________________________________________________________________ 15
MAX791
V
CC
GND
PFI
*OPTIONAL
R2
R3
R1
V
IN
+5V
C1*
TO µP
PFO
V
TRIP
= 1.25
R1 + R2
R2
V
H
= 1.25 /
R2
|| R3
VL - 1.25
+
5 - 1.25
=
1.25
R1 + R2
||
R3 R1 R3 R2
PFO
+5V
0V
0V V
H
V
TRIP
V
IN
V
L
Figure 14. Adding Hysteresis to the Power-Fail Comparator
MAX791
V
OUT
GND
CE IN
CE
CE
CE OUT
CE
CE
CE
CE
CE
CE
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMs.
MINIMUM Rp VALUE IS 1k
ACTIVE-HIGH CE
LINES FROM LOGIC
RAM 1
RAM 2
RAM 3
RAM 4
Rp*
Figure 13. Alternate CE Gating

MAX791ESE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits MPU Supervisor
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