89HPES3T3ZBBCG Datasheet 89HPES3T3ZBBCG, 89HPES3T3ZBBCGI, 89HPES3T3ZBBCG8 | P4-P6

4 of 31 June 12, 2014

IDT 89HPES3T3 Data Sheet

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

GPIO[9] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P3RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 3

Table 3 General Purpose I/O Pins

Signal Type Name/Description

APWRDISN I Auxiliary Power Disable Input. When this pin is active, it disables the

device from using auxiliary power supply.

CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be override by modifying the SCLK bit in the downstream

port’s PCIELSTS register.

CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the PA_PCIELSTS register.

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the

PES3T3 and initiates a PCI Express fundamental reset.

Table 4 System Pins (Part 1 of 2)

5 of 31 June 12, 2014

IDT 89HPES3T3 Data Sheet

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental

reset, the PES3T3 executes the reset procedure and remains in a reset

state with the Master SMBus active. This allows software to read and write

registers internal to the device before normal device operation begins. The

device exits the reset state when the RSTHALT bit is cleared in the

PA_SWCTL register by the SMBus master.

SWMODE[2:0] I Switch Mode. These configuration pins determine the PES3T3 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0xF Reserved

WAKEN I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN

signal input/output selection can be made through WAKEDIR bit setting in

the WAKEUPCNTL register.

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 5 Test Pins

Signal Type Name/Description

CORE I Core VDD. Power supply for core logic.

I/O I I/O VDD. LVTTL I/O buffer power supply.

PE I PCI Express Digital Power. PCI Express digital power used by the digital

power of the SerDes.

APE I PCI Express Analog Power. PCI Express analog power used by the PLL

and bias generator.

PE I PCI Express Termination Power.

I Ground.

Table 6 Power and Ground Pins

Signal Type Name/Description

Table 4 System Pins (Part 2 of 2)

6 of 31 June 12, 2014

IDT 89HPES3T3 Data Sheet

Pin Characteristics

Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.

This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left

floating can cause a slight increase in power consumption.

Function Pin Name Type Buffer

I/O

Type

Internal

Resistor

Notes

PCI Express Inter-

face

PE0RN[0] I CML Serial Link

PE0RP[0] I

PE0TN[0] O

PE0TP[0] O

PE2RN[0] I

PE2RP[0] I

PE2TN[0] O

PE2TP[0] O

PE3RN[0] I

PE3RP[0] I

PE3TN[0] O

PE3TP[0] O

PEREFCLKN I LVPECL/

CML

Diff. Clock

Input

Refer toTable 8

PEREFCLKP I

SMBus MSMBCLK I/O LVTTL STI

Schmitt Trigger Input (STI).

MSMBDAT I/O STI

General Purpose I/O GPIO[9,7,2:0] I/O LVTTL High Drive pull-up

System Pins APWRDISN I LVTTL Input pull-down

CCLKDS I pull-up

CCLKUS I pull-up

PERSTN I

RSTHALT I pull-down

SWMODE[2:0] I pull-down

WAKEN I/O open-drain

EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up

JTAG_TDI I STI pull-up

JTAG_TDO O

JTAG_TMS I STI pull-up

JTAG_TRST_N I STI pull-up

Table 7 Pin Characteristics

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

89HPES3T3ZBBCG

Mfr. #:

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Description:

PCI Interface IC PCI EXPRESS SWITCH

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89HPES3T3ZBBCG

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