8 of 31 June 12, 2014
IDT 89HPES3T3 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
AC Timing Characteristics
Parameter Description Min Typical Max Unit
PEREFCLK
Refclk
FREQ
Input reference clock frequency range 100 MHz
Refclk
DC
1
1.
ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
Duty cycle of input clock 40 50 60 %
T
R
, T
F
Rise/Fall time of input clocks 0.2*RCUI RCUI
2
2.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
V
SW
Differential input voltage swing
3
3.
AC coupling required.
0.6 1.6 V
T
jitter
Input clock jitter (cycle-to-cycle) 125 ps
Table 8 Input Clock Requirements
Parameter Description Min
1
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Typical
1
Max
1
Units
PCIe Transmit
UI Unit Interval 399.88 400 400.12 ps
T
TX-EYE
Minimum Tx Eye Width 0.7 .9 UI
T
TX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
0.15 UI
T
TX-RISE,
T
TX-FALL
D+ / D- Tx output rise/fall time 50 90 ps
T
TX- IDLE-MIN
Minimum time in idle 50 UI
T
TX-IDLE-SET-TO-
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20 UI
T
TX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data 20 UI
T
TX-SKEW
Transmitter data skew between any 2 lanes 500 1300 ps
T
BTEn
Time from asserting Beacon TxEn to beacon being trans-
mitted on the lane
30 80 ns
PCIe Receive
UI Unit Interval 399.88 400 400.12 ps
T
RX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance) 0.4 UI
T
RX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation 0.3 UI
T
RX-IDLE-DET-DIFF-
ENTER TIME
Unexpected Idle Enter Detect Threshold Integration Time 10 ms
T
RX-SKEW
Lane to lane input skew 20 ns
Table 9 PCIe AC Timing Characteristics
