LTC3603
13
3603fc
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applications inForMation
In order to turn on the topside MOSFET, the voltage on
the BOOST pin is then applied to its gate. As the topside
MOSFET turns on, the SW pin rises to the PV
IN
voltage
and the BOOST pin rises to PV
IN
+ INTV
CC
, thereby keep-
ing the MOSFET fully enhanced. For most applications, a
0.22µF ceramic capacitor is appropriate for C
BST
. Schottky
diode D
BST
should have a reverse breakdown voltage that
is greater than PV
IN(MAX)
.
A 1.2µA internal pull-up current will charge this capacitor,
resulting in a soft-start ramp time given by:
t
SS
= C
SS
0.6V
1.2µA
When the LTC3603 detects a fault condition (either
undervoltage lockout or overtemperature), the TRACK/SS
pin is quickly pulled to ground and the internal soft-start
timer is also reset. This ensures an orderly restart when
using an external soft-start capacitor.
To implement tracking, a resistor divider is placed between
an external supply (V
X
) and the TRACK/SS pin as shown
in Figure 5a. This technique can be used to cause V
OUT
to
ratiometrically track the V
X
supply (Figure 5b), according
to the following:
V
OUT
V
X
=
R
TA
R
A
R
A
+R
B
R
TA
+R
TB
For coincident tracking, as shown in Figure 5c, (V
OUT
=
V
X
during start-up),
R
TA
= R
A
, R
TB
= R
B
Note that the 1.2µA current that is sourced from the
TRACK/SS pin will cause a slight offset in the voltage seen
on the TRACK/SS pin and consequently on the V
OUT
volt-
age during tracking. This V
OUT
offset due to the TRACK/SS
current is given by:
V
OS,TRK
= (1µA)
R
TA
R
TA
R
TA
+R
TB
R
A
+R
B
R
A
For most applications, this offset is small and has minimal
effect on tracking performance. For improved tracking ac-
curacy, reduce the parallel impedance of R
TA
and R
TB
.
4.7MΩ
LTC3603
3603 F04
PV
IN
RUN
LTC3603
3.3V OR 5V
50k
RUN
R
B
LTC3603
R
A
3603 F05a
TRACK/SS
V
FB
V
OUT
R
TB
R
TA
V
X
Figure 4. RUN Pin Interfacing
Figure 5a. Using the TRACK/SS Pin to Track V
X
D
BST
LTC3603
C
BST
3603 F03
BOOST
SW
INTV
CC
C
INTVCC
Figure 3. Topside MOSFET Supply
Run and Soft-Start/Tracking Functions
The LTC3603 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 0.7V
puts the LTC3603 into a low quiescent current shutdown
mode (I
Q
< 1µA). When the RUN pin is greater than 0.7V,
the controller is enabled. The RUN pin can be driven directly
from logic as shown in Figure 4. Do not allow the RUN pin
to float during power cycling. In some cases, a pull-down
resistor of 50k or less may be needed to avoid this.
Soft-start and tracking are implemented by limiting the
effective reference voltage as seen by the error amplifier.
Ramping up the effective reference into the error amp in
turn causes a smooth and controlled ramp on the output
voltage of the converter. To use the default, internal 1ms
soft-start ramp, leave the TRACK/SS pin floating. Do not
tie the TRACK/SS pin to INTV
CC
or to PV
IN
. To increase the
soft-start time above 1ms, place a cap on the TRACK/SS pin.
LTC3603
14
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Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although
all
dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
operating current and I
2
R losses.
The V
IN
operating current loss dominates the efficiency loss
at very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents.
1. The V
IN
operating current comprises three components:
The DC supply current as given in the electrical char-
acteristics, the internal MOSFET gate charge currents
and the internal topside MOSFET transition losses. The
MOSFET gate charge current results from switching the
gate capacitance of the internal power MOSFET switches.
The gates of these switches are driven from the INTV
CC
supply. Each time the gate is switched from high to
low to high again, a packet of charge, dQ, moves from
INTV
CC
to ground. The resulting dQ/dt is the current
out of INTV
CC
that is typically larger than the DC bias
current. In continuous mode, the gate charge current
can be approximated by I
GATECHG
= f(9.5nC). Since the
INTV
CC
voltage is generated from V
IN
by a linear regula-
tor, the current that is internally drawn from the INTV
CC
supply can be treated as V
IN
current for the purposes
of efficiency considerations.
Transition losses apply only to the internal topside
MOSFET and become more prominent at higher input
voltages. Transition losses can be estimated from:
Transition Loss = (1.7) V
IN
2
• I
O(MAX)
• (120pF) • f
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. In
continuous mode, the average output current flow-
ing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current:
I
2
R Loss = I
O
2
(R
SW
+ R
L
)
Other losses, including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses, generally account for
less than 2% of the total power loss.
Thermal Considerations
In most applications, the LTC3603 does not dissipate much
heat due to its high efficiency. But, in applications where the
LTC3603 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
TIME
Figure 5b. Ratiometric Tracking
V
X
V
OUT
OUTPUT VOLTAGE
TIME
3603 F05b,c
Figure 5c. Coincident Tracking
V
X
V
OUT
OUTPUT VOLTAGE
LTC3603
15
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applications inForMation
To prevent the LTC3603 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
) • (θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3603 in dropout at an
input voltage of 8V, a load current of 2.5A and an ambient
temperature of 70°C. From the Typical Performance graph
of Switch Resistance, the R
DS(ON)
of the top switch at 70°C
is approximately 85mΩ. Therefore, power dissipated by
the part is:
P
D
= (I
LOAD
2
)(R
DS(ON)
) = (2.5A)
2
(85mΩ) = 0.53W
For the MSOP package, the θ
JA
is 45°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.53W)(45°C/W) = 93.85°C
which is below the maximum junction temperature of
125°C.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to DI
LOAD
•(ESR), where ESR is the effective series
resistance of C
OUT
. DI
LOAD
also begins to charge or dis-
charge C
OUT
, generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem. The I
TH
pin external components and output capacitor shown in the
front page application will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3603 in
an application with the following specifications: V
IN
=
12V, V
OUT
= 3.3V, I
OUT(MAX)
= 2.5A, I
OUT(MIN)
= 100mA,
f = 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
R
OSC
=
1.15 10
11
1MHz
10k = 105k
Next, calculate the inductor value for about 40% ripple
current at maximum V
IN
:
L =
3.3V
1MHz
( )
1A
( )
1–
3.3V
12V
= 2.39µH
Using a 2.2µH inductor results in a maximum ripple cur-
rent of:
ΔI
L
=
3.3V
1MHz
( )
2.2µH
( )
1–
3.3V
12V
= 1.1A
C
OUT
will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. In this applica
-
tion, a tantalum capacitor will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower
the total effective ESR. For this design, a 100µF ceramic
capacitor will be used. C
IN
should be sized for a maximum
current rating of:
I
RMS
= 2.5A
3.3V
12V
12V
3.3V
1= 1.12A
RMS
Decoupling the PV
IN
pin with a 22µF ceramic capacitor is
adequate for most applications.
The output voltage can now be programmed by choosing
the values of R1 and R2. Choose R1 = 105k and calculate
R2 as:
R2= R1
V
OUT
0.6V
1
= 472.5k

LTC3603EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2.5A, 15V Mono Sync Buck Reg
Lifecycle:
New from this manufacturer.
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