NCP3155A, NCP3155B
http://onsemi.com
10
DETAILED DESCRIPTION
OVERVIEW
The NCP3155A/B operates as a 500 kHz/1.0 MHz, voltage
mode, pulse width modulated, (PWM) synchronous buck
converter. It drives high−side and low−side N−channel power
MOSFETs. The NCP3155 incorporates an internal boost
circuit consisting of a boost clamp and boost diode to provide
supply voltage for the high side MOSFET gate driver. The
NCP3155 also integrates several protection features including
input undervoltage lockout (UVLO), output undervoltage
(OUV), output overvoltage (OOV), adjustable high−side
current limit (I
SET
and I
LIM
), and thermal shutdown (TSD).
The operational transconductance amplifier (OTA)
provides a high gain error signal from Vout which is
compared to the internal 1.5 V pk-pk ramp signal to set the
duty cycle converter using the PWM comparator. The high
side switch is turned on by the positive edge of the clock
cycle going into the PWM comparator and flip flop
following a non-overlap time. The high side switch is turned
off when the PWM comparator output is tripped by the
modulator ramp signal reaching a threshold level
established by the error amplifier. The gate driver stage
incorporates fixed non− overlap time between the high−side
and low−side MOSFET gate drives to prevent cross
conduction of the power MOSFET’s.
POR and UVLO
The device contains an internal Power On Reset (POR) and
input Undervoltage Lockout (UVLO) that inhibits the internal
logic and the output stage from operating until V
CC
reaches its
respective predefined voltage levels (4.3 V typical).
Startup and Shutdown
Once V
CC
crosses the UVLO rising threshold the device
begins its startup process. Closed−loop soft−start begins
after a 400 ms delay wherein the boost capacitor is charged,
and the current limit threshold is set. During the 400 ms delay
the OTA output is set to just below the valley voltage of the
internal ramp. This is done to reduce delays and to ensure a
consistent pre−soft−start condition. The device increases the
internal reference from 0 V to 0.8 V in 32 discrete steps
while maintaining closed loop regulation at each step. Each
step contains 32 switching cycles. Some overshoot may be
evident at the start of each step depending on the voltage
loop phase margin and bandwidth. The total soft−start time
is 2.4 ms for the NCP3155A and 1.2 ms for the NCP3155B.
Figure 30. Soft−Start Details
Internal Reference Voltage
25 mV Steps
0.8 V
0V
0 .7V
OTA Output
Internal Ramp
Output Voltage
32 Voltage Steps
