NCP3155A, NCP3155B
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19
Output Capacitor Selection
The important factors to consider when selecting an
output capacitor is dc voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be rated to handle the ripple
current at full load with proper derating. The RMS ratings
given in datasheets are generally for lower switching
frequency than used in switch mode power supplies but a
multiplier is usually given for higher frequency operation.
The RMS current for the output capacitor can be calculated
below:
Co
RMS
+ I
O
@
ra
12
Ǹ
(eq. 17)
The maximum allowable output voltage ripple is a
combination of the ripple current selected, the output
capacitance selected, the equivalent series inductance (ESL)
and ESR.
The main component of the ripple voltage is usually due to
the ESR of the output capacitor and the capacitance selected.
V
ESR_C
+ I
O
@ ra @
ǒ
ESR
Co
)
1
8 @ F
SW
@ Co
Ǔ
(eq. 18)
The ESL of capacitors depends on the technology chosen
but tends to range from 1 nH to 20 nH where ceramic
capacitors have the lowest inductance and electrolytic
capacitors then to have the highest. The calculated
contributing voltage ripple from ESL is shown for the switch
on and switch off below:
V
ESLON
+
ESL @ I
PP
@ F
SW
D
(eq. 19)
V
ESLOFF
+
ESL @ I
PP
@ F
SW
(
1 * D
)
(eq. 20)
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initially drops
due to the current variation inside the capacitor and the ESR
(neglecting the effect of the effective series inductance (ESL)).
DV
OUTESR
+ DI
TRAN
@ ESR
Co
(eq. 21)
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is
approximated by the following equation:
DV
OUTDISCHG
+
ǒ
I
TRAN
Ǔ
2
@ L
OUT
C
OUT
@
ǒ
V
IN
* V
OUT
Ǔ
(eq. 22)
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. It should be noted
that DVOUTDISCHARGE and DVOUTESR are out of
phase with each other, and the larger of these two voltages
will determine the maximum deviation of the output voltage
(neglecting the effect of the ESL).
Conversely during a load release, the output voltage can
increase as the energy stored in the inductor dumps into the
output capacitor. The ESR contribution from Equation 18
still applies in addition to the output capacitor charge which
is approximated by the following equation:
DV
OUTCHG
+
ǒ
I
TRAN
Ǔ
2
@ L
OUT
C
OUT
@ V
OUT
(eq. 23)
As with any power design, proper laboratory testing should
be performed to insure the design will dissipate the required
power under worst case operating conditions. Variables
considered during testing should include maximum ambient
temperature, minimum airflow, maximum input voltage,
maximum loading, and component variations.
Feedback and Compensation
The NCP3155 is a voltage mode buck convertor with a
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°). The transfer
function of the power stage (the output LC filter) is a double
pole system. The resonance frequency of this filter is
expressed as follows:
f
P0
+
1
2 @ p @ L @ C
OUT
Ǹ
(eq. 24)
Parasitic Equivalent Series Resistance (ESR) of the
output filter capacitor introduces a high frequency zero to
the filter network. Its value can be calculated by using the
following equation:
f
Z0
+
1
2 @ p @ C
OUT
@ ESR
(eq. 25)
The main loop zero crossover frequency f0 can be chosen
to be 1/10 1/5 of the switching frequency. Table 2 shows
the three methods of compensation.
Table 2. COMPENSATION TYPES
Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type
f
P0
< f
Z0
< f
0
< f
S
/2 Type II Electrolytic, Tantalum
f
P0
< f
0
< f
Z0
< f
S
/2 Type III Method I Tantalum, Ceramic
f
P0
< f
0
< f
S
/2 < f
Z0
Type III Method II Ceramic
NCP3155A, NCP3155B
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Compensation Type II
This compensation is suitable for electrolytic capacitors.
Components of the Type II (Figure 42) network can be
specified by the following equations:
Figure 42. Type II Compensation
R
C1
+
2 @ p @ f
0
@ L @ V
RAMP
@ V
OUT
ESR @ V
IN
@ V
ref
@ gm
(eq. 26)
C
C1
+
1
0.75 @ 2 @ p @ f
P0
@ R
C1
(eq. 27)
C
C2
+
1
p @ R
C1
@ f
S
(eq. 28)
R1 +
V
OUT
* V
ref
V
ref
@ R2
(eq. 29)
V
RAMP
is the peaktopeak voltage of the oscillator ramp
and gm is the transconductance error amplifier gain.
Capacitor C
C2 is optional.
Compensation Type III
Tantalum and ceramics capacitors have lower ESR than
electrolytic, so the zero of the output LC filter goes to a
higher frequency above the zero crossover frequency. This
requires a Type III compensation network as shown in
Figure 43.
There are two methods to select the zeros and poles of this
compensation network. Method I is ideal for tantalum
output capacitors, which have a higher ESR than ceramic:
Figure 43. Type III Compensation
f
Z1
+ 0.75 @ f
P0
(eq. 30)
f
Z2
+ f
P0
(eq. 31)
f
P2
+ f
Z0
(eq. 32)
f
P3
+
f
S
2
(eq. 33)
Method II is better suited for ceramic capacitors that
typically have the lowest ESR available:
f
Z2
+ f
0
@
1 * sinq max
1 ) sin q max
Ǹ
(eq. 34)
f
P2
+ f
0
@
1 ) sin q max
1 * sin q max
Ǹ
(eq. 35)
f
Z1
+ 0.5 @ f
Z2
(eq. 36)
f
P3
+ 0.5 @ f
S
(eq. 37)
qmax is the desired maximum phase margin at the zero
crossover frequency, ƒ
0
. It should be 45° 75°. Convert
degrees to radians by the formula:
q max + q max
degress
@
ǒ
2 @ p
360
Ǔ
:Units+ radians
(eq. 38)
The remaining calculations are the same for both methods.
R
C1
uu
2
gm
(eq. 39)
C
C1
+
1
2 @ p @ f
Z1
@ R
C1
(eq. 40)
C
C2
+
1
2 @ p @ f
P3
@ R
C1
(eq. 41)
C
FB1
+
2 @ p @ f
0
@ L @ V
RAMP
@ C
OUT
V
IN
@ R
C1
(eq. 42)
R
FB1
+
1
2p @ C
FB1
@ f
P2
(eq. 43)
R1 +
1
2 @ p @ C
FB1
@ f
Z2
* R
FB1
(eq. 44)
R2 +
V
ref
V
OUT
* V
ref
@ R1
(eq. 45)
If the equation in Equation 46 is not true, then a higher value
of R
C1
must be selected.
R1 @ R2 @ R
FB1
R1 @ R
FB1
) R2 @ R
FB1
) R1 @ R2
u
1
gm
(eq. 46)
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21
Output Current Derating
The NCP3155 has a wide input voltage and output voltage
capability. It also operates in a variety of thermal
environments. These thermal conditions limit the maximum
output current for a given input and output voltage.
Therefore, proper output current derating must be
considered, taking into account ambient temperature,
airflow, the input and output conditions, and the need for
increased reliability. Figures 24 29 show safe operating
conditions vs. output current for input voltages of 12 V,
18 V, and 24 V. These curves assumed 300 mm
2
of 2 oz
copper. Sufficient cooling could also be provided to ensure
reliable operation. Finally, to maintain operation in the safe
operating areas shown in the curves, it is recommended to
use the NCP3155 with input to output conditions as shown
in Figure 44.
Figure 44. Recommended Maximum Output
Voltage vs Input Voltage
0
2
4
6
8
10
12
14
4 6 8 1012141618202224
V
IN
, INPUT VOLTAGE (V)
V
OUT
, OUTPUT VOLTAGE (V)

NCP3155ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG BUCK ADJUSTABLE 3A 8SOIC
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