R8C/36T-A Group 2. Central Processing Unit (CPU)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3.
R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers.
The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0).
Similarly, R3 and R1 can be used as a 32-bit data register.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5 Program Counter (PC)
PC is a 20-bit register that indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. It must only be set to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0.
R8C/36T-A Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I
flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware
interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is
executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has
higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
The write value must be 0. The read value is undefined.
R8C/36T-A Group 3. Address Space
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3. Address Space
3.1 Memory Map
Figure 3.1 shows the Memory Map. The R8C/36T-A Group has a 1-Mbyte address space from addresses 00000h to
FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower addresses, beginning with
address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses, beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
Figure 3.1 Memory Map
0XXXXh
00000h
Internal ROM
(program ROM)
Internal RAM
SFR
Internal ROM
(data flash)
(1)
002FFh
00400h
07000h
07FFFh
0YYYYh
0FFFFh
FFFFFh
Watchdog timer, oscillation stop detection, voltage monitor
Undefined instruction
Overflow
BRK instruction
Address match
Single-step
Address break
(Reserved)
Reset
0FFFFh
0FFDCh
Internal ROM
(program ROM)
ZZZZZh
06FFFh
06800h
SFR
(2)
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the ELC, DTC, and TSCU SFR areas.
3. The blank areas are reserved. No access is allowed.
Part Number
Capacity
Address 0YYYYh
Internal ROM
Address 0XXXXh
Capacity
Internal RAM
Address ZZZZZh
64 Kbytes
96 Kbytes
128 Kbytes
08000h
08000h
08000h
17FFFh
1FFFFh
27FFFh
01BFFh
023FFh
02BFFh
6 Kbytes
8 Kbytes
10 Kbytes
R5F21368SNFP/FA, R5F21368SDFP/FA
R5F21368SNFP/FA, R5F21368SDFP/FA
R5F21368SNFP/FA, R5F21368SDFP/FA

R5F2136CSNFP#30

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU R8C/36TA 128+4K/10K 64LQFP
Lifecycle:
New from this manufacturer.
Delivery:
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