R8C/36T-A Group 4. Electrical Characteristics
R01DS0055EJ0100 Rev.1.00 Page 37 of 58
Dec 09, 2011
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-
byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C.
Table 4.5 Flash Memory (Program ROM) Characteristics
(Vcc = 2.7 V to 5.5 V, Topr =20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Symbol Parameter Conditions
Standard
Unit
Min. Typ. Max.
Program/erase endurance
(1)
1,000
(2)
――times
Byte program time
(Program and erase endurance
100
times)
―― μs
Byte program time
(Program and erase endurance
1,000
times)
―― μs
Word program time
(Program and erase endurance
100
times)
Topr = 25°C,
VCC = 5.0 V
100 200 μs
Word program time
(Program and erase endurance
100
times)
100 400 μs
Word program time
(Program and erase endurance
1,000
times)
100 650 μs
Block erase time 0.3 4 s
t
d(SR-SUS) Time delay from suspend request until
suspend
――5 + CPU clock
× 3 cycles
ms
Interval from erase start/restart until
following suspend request
0 ――μs
Time from suspend until erase restart ――30 + CPU clock
× 1 cycle
μs
t
d(CMDRST
-READY)
Time from when command is forcibly
terminated until reading is enabled
――30 + CPU clock
× 1 cycle
μs
Program, erase voltage 2.7 5.5 V
Read voltage 1.8 5.5 V
Program, erase temperature
20 (N ver.)
40 (D ver.)
85 °C
Data hold time
(6)
Ambient temperature
= 55°C
(7)
20 ――year
R8C/36T-A Group 4. Electrical Characteristics
R01DS0055EJ0100 Rev.1.00 Page 38 of 58
Dec 09, 2011
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100, 1,000 or 10,000), each block can be erased n times. For example, if
1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. The data hold time includes 7,000 hours under an environment of ambient temperature 85°C.
Table 4.6 Flash Memory (Data flash Block A to Block D) Characteristics
(Vcc = 2.7 V to 5.5 V, Topr = 20°C to 85°C (N version)/40°C to 85°C (D version),
unless otherwise specified)
Symbol Parameter Conditions
Standard
Unit
Min. Typ. Max.
Program/erase endurance
(1)
10,000
(2)
――times
Byte program time
(Program and erase endurance
1,000
times)
160 950 μs
Byte program time
(Program and erase endurance > 1,000
times)
300 950 μs
Block erase time
(Program and erase endurance
1,000
times)
0.2 1 s
Block erase time
(Program and erase endurance > 1,000
times)
0.3 1 s
t
d(SR-SUS) Time delay from suspend request until
suspend
――3 + CPU clock
× 3 cycles
ms
Interval from erase start/restart until
following suspend request
0 ――μs
Time from suspend until erase restart ――30 + CPU
clock
× 1 cycle
μs
t
d(CMDRST
-READY)
Time from when command is forcibly
terminated until reading is enabled
――30 + CPU
clock
× 1 cycle
μs
Program, erase voltage 2.7 5.5 V
Read voltage 1.8 5.5 V
Program, erase temperature
20 (N ver.)
40 (D ver.)
85 °C
Data hold time
(6)
Ambient temperature
= 55°C
(7)
20 ――year
R8C/36T-A Group 4. Electrical Characteristics
R01DS0055EJ0100 Rev.1.00 Page 39 of 58
Dec 09, 2011
Figure 4.2 Time Delay from Suspend Request until Suspend
Notes:
1. The voltage detection level must be selected with bits VDSEL0 and VDSEL1 in the OFS register.
2. Time until the voltage monitor 0 reset is generated after the voltage passes V
det0.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 4.7 Voltage Detection 0 Circuit Characteristics
(Measurement conditions: Vcc = 1.8 V to 5.5 V, Topr = 20°C to 85°C (N version)/
40°C to 85°C (D version))
Symbol Parameter Conditions
Standard
Unit
Min. Typ. Max.
V
det0
Voltage detection level Vdet0_0
(1)
When Vcc falls 1.80 1.90 2.05 V
Voltage detection level Vdet0_1
(1)
When Vcc falls 2.15 2.35 2.55 V
Voltage detection level Vdet0_2
(1)
When Vcc falls 2.70 2.85 3.05 V
Voltage detection level Vdet0_3
(1)
When Vcc falls 3.55 3.80 4.05 V
Voltage detection 0 circuit response time
(2)
At the falling of Vcc from 5 V
to (Vdet0
0.1) V
6 150 μs
Voltage detection circuit self power
consumption
VCA25 = 1, Vcc = 5.0 V 1.5 ―μA
t
d(E-A) Waiting time until voltage detection circuit
operation starts
(3)
――100 μs
FST6 bit
Suspend request
(FMR21 bit)
Fixed time
Clock-dependent
time
Access restart
FST6: Bit in FST register
FMR21: Bit in FMR2 register
t
d(SR-SUS)

R5F2136CSNFP#30

Mfr. #:
Manufacturer:
Renesas Electronics
Description:
16-bit Microcontrollers - MCU R8C/36TA 128+4K/10K 64LQFP
Lifecycle:
New from this manufacturer.
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