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8524AYLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Low Skew, 1-to-22
Differential-to-HSTL Fanout Buffer
8524
DATA SHEET
8524 REVISION B 11/9/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 8524 is a low skew, 1-to-22 Differential-to-HSTL
Fanout Buffer . The 8524 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The device is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the OE pin. The
8524’s low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high
performance clock distribution applications.
FEATURES
• Twenty-two differential HSTL outputs
each with the ability to drive 50Ω to ground
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to HSTL levels with resistor bias on nCLK input
• Output skew: 80ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Jitter, RMS: 0.04ps (typical)
• LVPECL and HSTL mode operating voltage supply range:
V
DD
= 3.3V ± 5%, V
DDO
= 1.6V to 2V, GND = 0V
• 0°C to 85°C ambient operating temperature
BLOCK DIAGRAM PIN ASSIGNMENT
CLK
nCLK
PCLK
nPCLK
Q0:Q21
nQ0:nQ21
LE
Q
D
CLK_SEL
OE
0
1
22
22
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ICS8524
VDDO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
DDO
VDDO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
VDDO
nQ13
Q13
nQ12
Q12
nQ11
Q11
nQ10
Q10
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
DDO
VDDO
nc
nc
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
OE
nc
nc
nQ21
Q21
V
DDO
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8524 DATA SHEET
2 REVISION B 11/9/15
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1, 16, 17, 32,
33, 48, 49, 64
V
DDO
Power Output supply pins.
2, 3, 12, 13 nc Unused No connect.
4V
DD
Power Core supply pin.
5 CLK Input Pulldown Non-inverting differential clock input pair.
6 nCLK Input
Pullup/
Pulldown
Inverting differential clock input pair. Biased to
2
/
3
V
CC
.
7 CLK_SEL Input Pullup
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
8 PCLK Input Pulldown Non-inverting differential LVPECL clock input pair.
9 nPCLK Input
Pullup/
Pulldown
Inverting differential LVPECL clock input pair. Biased to
2
/
3
V
CC
.
10 GND Power Power supply ground.
11 OE Input Pullup
Output enable. Controls enabling and disabling of outputs
Q0:Q21, nQ0:nQ21. LVCMOS / LVTTL interface levels.
14, 15 nQ21, Q21 Output Differential clock outputs. HSTL interface levels.
18, 19 nQ20, Q20 Output Differential clock outputs. HSTL interface levels.
20, 21 nQ19, Q19 Output Differential clock outputs. HSTL interface levels.
22, 23 nQ18, Q18 Output Differential clock outputs. HSTL interface levels.
24, 25 nQ17, Q17 Output Differential clock outputs. HSTL interface levels.
26, 27 nQ16, Q16 Output Differential clock outputs. HSTL interface levels.
28, 29 nQ15, Q15 Output Differential clock outputs. HSTL interface levels.
30, 31 nQ14, Q14 Output Differential clock outputs. HSTL interface levels.
34, 35 nQ13, Q13 Output Differential clock outputs. HSTL interface levels.
36, 37 nQ12, Q12 Output Differential clock outputs. HSTL interface levels.
38, 39 nQ11, Q11 Output Differential clock outputs. HSTL interface levels.
40, 41 nQ10, Q10 Output Differential clock outputs. HSTL interface levels.
42, 43 nQ9, Q9 Output Differential clock outputs. HSTL interface levels.
44, 45 nQ8, Q8 Output Differential clock outputs. HSTL interface levels.
46, 47 nQ7, Q7 Output Differential clock outputs. HSTL interface levels.
50, 51 nQ6, Q6 Output Differential clock outputs. HSTL interface levels.
52, 53 nQ5, Q5 Output Differential clock outputs. HSTL interface levels.
54, 55 nQ4, Q4 Output Differential clock outputs. HSTL interface levels.
56, 57 nQ3, Q3 Output Differential clock outputs. HSTL interface levels.
58, 59 nQ2, Q2 Output Differential clock outputs. HSTL interface levels.
60, 61 nQ1, Q1 Output Differential clock outputs. HSTL interface levels.
62, 63 nQ0, Q0 Output Differential clock outputs. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 11/9/15
8524 DATA SHEET
3 LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 37
KΩ
R
PULLDOWN
Input Pulldown Resistor 75
KΩ
Inputs Outputs
OE CLK_SEL Q0:Q21 nQ0:nQ21
0 0 LOW HIGH
0 1 LOW HIGH
1 0 CLK nCLK
1 1 PCLK nPCLK
FIGURE 1. OE TIMING DIAGRAM
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8524AYLF

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Buy 8524AYLF
Manufacturer:
IDT
Description:
Clock Buffer 22 HSTL OUT BUFFER
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