REVISION B 11/9/15
8524 DATA SHEET
13 LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 7.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R
L
) * (V
DDO_MAX
- V
OH_MIN
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DDO_MAX
- V
OL_MAX
)
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
FIGURE 7. HSTL DRIVER CIRCUIT AND TERMINATION
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8524 DATA SHEET
14 REVISION B 11/9/15
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 8524 is: 1474
TABLE 7. θ
JA
VS. AIR FLOW T ABLE FOR 64 LEAD TQFP, E-PAD
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 22.3°C/W 17.2°C/W 15.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION B 11/9/15
8524 DATA SHEET
15 LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
ACD-HD
MINIMUM NOMINAL MAXIMUM
N
64
A
-- -- 1.20
A1
0.05 0.10 0.15
A2
0.95 1.0 1.05
b
0.17 0.22 0.27
c
0.09 -- 0.20
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
e
0.50 BASIC
L
0.45 0.60 0.75
θ
0°
--
7°
ccc
-- -- 0.08
D3 & E3
2.0 -- 10.0
Thermal
Pad
Down
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, E-PAD

8524AYLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 22 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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