LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8524 DATA SHEET
4 REVISION B 11/9/15
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Power Supply Voltage 1.6 1.8 2.0 V
I
DD
Power Supply Current 220 mA
I
DDO
Output Supply Current No Load 1 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current OE, CLK_SEL 5 µA
I
IL
Input Low Current OE, CLK_SEL -150 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current CLK, nCLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current CLK, nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V
DD
- 0.85 V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
22.3°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
REVISION B 11/9/15
8524 DATA SHEET
5 LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
TABLE 4D. LVPECL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current PCLK, nPCLK V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current PCLK, nPCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.3 1 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 V
DD
V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 500 MHz
t
PD
Propagation Delay; NOTE 1 1.7 2.7 ns
tsk(o) Output Skew; NOTE 2, 4 80 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 700 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
0.04 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 300 700 ps
t
S
Setup Time 1.0 ns
t
H
Hold Time 0.5 ns
odc Output Duty Cycle
ƒ 133MHz 49 51 %
133 < ƒ 266MHz 48 52 %
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions at the same temperature. Using the same type of inputs on each device,
the outputs are measured at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 4E. HSTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 1.0 1.4 V
V
OL
Output Low Voltage; NOTE 1 0 0.4 V
V
OX
Output Crossover Voltage; NOTE 2 40 60 %
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.1 V
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defi ned with respect to output voltage swing at a given condition.
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8524 DATA SHEET
6 REVISION B 11/9/15
ADDITIVE PHASE JITTER
Input/Output Additive
Phase Jitter at 156.25MHz
= 0.04ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-
140
-150
-
160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specifi c offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specifi ed plot in many
applications. Phase noise is defi ned as the ratio of the noise
power present in a 1Hz band at a specifi ed offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
As with most timing specifi cations, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise fl oor of the equipment is higher
than the noise fl oor of the device. This is illustrated above. The
1Hz band to the power in the fundamental. When the required
offset is specifi ed, the phase noise is called a dBc value, which
simply means dBm at a specifi ed offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise fl oor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ

8524AYLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 22 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
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