19
Figure 24. Typical application circuit.
Figure 26. Waveforms for dead time calculation.Figure 25. Minimum LED skew for zero dead time.
0.1 µF
20 k
HCPL-4506 fig 28
CMOS
310
+5 V
V
OUT1
I
LED1
V
CC1
M
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
Q2
Q1
-HV
+HV
IPM
8
7
6
1
3
SHIELD
5
2
4
20 k
HCPL-4506
0.1 µF
20 k
CMOS
310
+5 V
V
OUT2
I
LED2
V
CC2
8
7
6
1
3
SHIELD
5
2
4
20 k
HCPL-4506
HCPL-4506 fig 29
V
OUT1
V
OUT2
I
LED2
t
PLH MAX.
PDD* MAX. =
(t
PLH-
t
PHL
)
MAX. =
t
PLH MAX. -
t
PHL MIN.
t
PHL
MIN.
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-4506 fig 30
V
OUT1
V
OUT2
I
LED2
t
PLH
MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (t
PLH MAX.
-
t
PLH MIN.
)
+
(t
PHL MAX.
-
t
PHL MIN.
)
= (t
PLH MAX.
-
t
PHL MIN.
) -
(t
PLH MIN.
-
t
PHL MAX.
)
= PDD* MAX. - PDD* MIN.
t
PHL
MIN.
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
t
PLH
MAX.
t
PHL
MAX.
PDD*
MAX.
MAX.
DEAD TIME
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
20
LED Drive Circuit Considerations for Ultra High CMR Performance
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupl-ing from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 16. The HCPL-4506
series improve CMR performance by using a detector
IC with an optically transparent Faraday shield, which
diverts the capacitively coupled current away from the
sensitive IC circuitry. However, this shield does not elimi-
nate the capacitive coupling between the LED and the
optocoupler output pins and output ground as shown in
Figure 17. This capacitive coupling causes perturbations
in the LED current during common mode transients and
becomes the major source of CMR failures for a shielded
optocoupler. The main design objective of a high CMR
LED drive circuit becomes keeping the LED in the proper
state (on or o) during common mode transients. For ex-
ample, the recommended application circuit (Figure 15),
can achieve 15 kV/µs CMR while minimizing component
complexity. Note that a CMOS gate is recommended in
Figure 15 to keep the LED o when the gate is in the high
state.
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
C
LEDO1
and C
LEDO2
in Figure 17. Many factors inuence
the eect and magnitude of the direct coupling includ-
ing: the use of an internal or external output pull-up re-
sistor, the position of the LED current setting resistor, the
connection of the unused input package pins, and the
value of the capacitor at the optocoupler output (C
L
).
Techniques to keep the LED in the proper state and mini-
mize the eect of the direct coupling are discussed in the
next two sections.
CMR with the LED On (CMR
L
)
A high CMR LED drive circuit must keep the LED on dur-
ing common mode transients. This is achieved by over-
driving the LED current beyond the input threshold so
that it is not pulled below the threshold during a tran-
sient. The recommended minimum LED current of 10 mA
provides adequate margin over the maximum I
TH
of
5.0 mA (see Figure 1) to achieve 15 kV/µs CMR. Capacitive
coupling is higher when the internal load resistor is used
(due to C
LEDO2
) and an I
F
= 16 mA is required to obtain
10 kV/µs CMR.
The placement of the LED current setting resistor eects
the ability of the drive circuit to keep the LED on dur-
ing transients and interacts with the direct coupling to
the optocoupler output. For example, the LED resistor in
Figure 18 is connected to the anode. Figure 19 shows the
AC equivalent circuit for Figure 18 during common mode
transients. During a +dVcm/dt in Figure 19, the current
available at the LED anode (Itotal) is limited by the series
resistor. The LED current (I
F
) is reduced from its DC value
by an amount equal to the current that ows through
C
LEDP
and C
LEDO1
. The situation is made worse because
the current through C
LEDO1
has the eect of trying to pull
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the
recommended LED drive circuit (Figure 15) places the
current setting resistor in series with the LED cathode.
Figure 20 is the AC equivalent circuit for Figure 15 during
common mode transients. In this case, the LED current
is not reduced during a +dVcm/dt transient because the
current owing through the package capacitance is sup-
plied by the power supply. During a -dVcm/dt transient,
however, the LED current is reduced by the amount of
current owing through C
LEDN
. But, better CMR perfor-
mance is achieved since the current owing in C
LEDO1
during a negative transient acts to keep the output low.
Coupling to the LED and output pins is also aected by
the connection of pins 1 and 4. If CMR is limited by per-
turbations in the LED on current, as it is for the recom-
mended drive circuit (Figure 15), pins 1 and 4 should be
connected to the input circuit common. However, if CMR
performance is limited by direct coupling to the output
when the LED is o, pins 1 and 4 should be left uncon-
nected.
CMR with the LED O (CMR
H
)
A high CMR LED drive circuit must keep the LED o
(V
F
V
F(OFF)
) during common mode transients. For ex-
ample, during a +dVcm/dt transient in Figure 20, the
current owing through C
LEDN
is supplied by the parallel
combination of the LED and series resistor. As long as the
voltage developed across the resistor is less than V
F(OFF)
the LED will remain o and no common mode failure will
occur. Even if the LED momentarily turns on, the 100 pF
capacitor from pins 6-5 will keep the output from dip-
ping below the threshold. The recommended LED drive
circuit (Figure 15) provides about 10 V of margin between
the lowest optocoupler output voltage and a 3 V IPM
threshold during a 15 kV/µs transient with V
CM
= 1500 V.
Additional margin can be obtained by adding a diode
in parallel with the resistor, as shown by the dashed line
connection in Figure 20, to clamp the voltage across the
LED below V
F(OFF)
.
Since the open collector drive circuit, shown
in Figure 21, cannot keep the LED o during
a +dVcm/dt transient, it is not desirable for applications
requiring ultra high CMR
H
performance. Figure 22 is the
AC equivalent circuit for Figure 21 during common mode
transients. Essentially all the current owing through
C
LEDN
during a +dVcm/dt transient must be supplied by
the LED. CMR
H
failures can occur at dV/dt rates where
the current through the LED and C
LEDN
exceeds the input
threshold. Figure 23 is an alternative drive circuit which
does achieve ultra high CMR performance by shunting
the LED in the o state.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0551EN
AV02-1360EN - June 20, 2008
IPM Dead Time and Propagation Delay Specications
The HCPL-4506 series include a Propagation Delay Dier-
ence specication intended to help designers minimize
dead time” in their power inverter designs. Dead time is
the time period during which both the high and low side
power transistors (Q1 and Q2 in Figure 24) are o. Any
overlap in Q1 and Q2 conduction will result in large cur-
rents owing through the power devices between the
high and low voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the IPM IGBT gate
drive circuit can be analyzed in the same way) it is impor-
tant to know the minimum and maximum turn-on (t
PHL
)
and turn-o (t
PLH
) propagation delay specications, pref-
erably over the desired operating temperature range.
The limiting case of zero dead time occurs when the in-
put to Q1 turns o at the same time that the input to
Q2 turns on. This case determines the minimum de-
lay between LED1 turn-o and LED2 turn-on, which
is related to the worst case optocoupler propagation
delay waveforms, as shown in Figure 25. A minimum
dead time of zero is achieved in Figure 25 when the
signal to turn on LED2 is delayed by (t
PLH max
- t
PHL
min
) from the LED1 turn o. Note that the propagation
delays used to calculate PDD are taken at equal tem-
peratures since the optocouplers under consideration
are typically mounted in close proximity to each other.
(Specically, t
PLH max
and t
PHL min
in the previous equa-
tion are not the same as the t
PLH max
and t
PHL min
, over the
full operating temperature range, specied in the data
sheet.) This delay is the maximum value for the propaga-
tion delay dierence specication which is specied at
450 ns for the HCPL-4506 series over an operating tem-
perature range of
-40°C to 100°C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time
is zero, but it does not tell a designer what the maxi-
mum dead time will be. The maximum dead time oc-
curs in the highly unlikely case where one optocoupler
with the fastest t
PLH
and another with the slowest t
PHL
are in the same inverter leg. The maximum dead
time in this case becomes the sum of the spread
in the t
PLH
and t
PHL
propagation delays as shown in Figure 26.
The maximum dead time is also equivalent to the dier-
ence between the maximum and minimum propagation
delay dierence specications. The maximum dead time
(due to the optocouplers) for the HCPL-4506 series is
600 ns (= 450
ns - (-150 ns) ) over an operating tempera-
ture range of -40°C to 100°C.

HCPL-4506-300E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers 1MBd 1Ch 10mA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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