XRD98L59
16
Rev. 2.00
Figure 10. Timing Diagram of the CDS Clocks and Internal Signals (RSTREJ,
φφ
φφ
φ1
, ,
, ,
,
φφ
φφ
φ2, ADCCLK
))
))
)
SDI = 0011 0100 1100
* Digital Output Data is Updated on the Falling Edge of
φφ
φφ
φ2.
This Update Position is Affected by the Aperture Delay of
φφ
φφ
φ2.
Note: Aperture Delay is not Shown
CCD
RSTREJ
SBLK
SPIX
φ
1
φ
2
(Internal Signals)
ADCLK
HOLD TRACK
Reset
Phase
Black
Reference
Phase
Video
Phase
DB[9:0]*
17
Rev. 2.00
XRD98L59
D4 D3 D2
φφ
φφ
φ2 Aperture Delay
0 0 0 2.7ns (default)
0 0 1 4.7ns
0 1 0 6.7ns
0 1 1 8.7ns
1 0 0 10.7ns
1 0 1 12.7ns
1 1 0 14.7ns
1 1 1 16.7ns
Table 14. Programmable
φφ
φφ
φ2 Delays
D7 D6 D5
φφ
φφ
φ1 Aperture Delay
0 0 0 3.5ns (default)
0 0 1 5.5ns
0 1 0 7.5ns
0 1 1 9.5ns
1 0 0 11.5ns
1 0 1 13.5ns
1 1 0 15.5ns
1 1 1 17.5ns
Table 13. Programmable
φφ
φφ
φ1 Delays
SBLK and SPIX Programmable Aperture Delay
(SDI Address = 0010)
The positioning of φ1 and φ2 from Figure 10, are opti-
mized by using a programmable aperture delay function.
φ1 and φ2 are delayed internally by the amount specified
in the serial port. SBLK delay (D7:D5) delays the φ1
clock and SPIX delay (D4:D2) delays the φ2 clock. The
delay is 2ns per lsb. The aperture delays t
BK
and t
VD
are
added to the programmable aperture delay to determine
final positioning. The tables below include the t
BK
and t
VD
aperture delays.
The aperture delay of φ2 also delays the output data bus
DB[9:0]. Digital output data is updated on the falling
edge of φ2 as shown in Figure 10. Data is valid after t
DL
plus the change in φ2 aperture delay. For example, if
D[4:2] equals 001b, then data is valid at t
DL
+ 2ns. (t
DL
is shown in Figure 6).
XRD98L59
18
Rev. 2.00
Figure 11. End of Line OB Pixels Used for
Line Calibration Mode on a Typical CCD Array
Active Pixels
End of LIne
OB
Calibration
Pixels
LINE CALIBRATION MODE
Line calibration mode calibrates during the OB pixel
output from the CCD at the end of every line. Figure 11,
shows the outline of a typical CCD area array. The
active (white) pixels are shown with the OB (shaded)
pixels around the edges. The OB pixels used in line
calibration are identified below in Figure 11 as the dark
shaded OB pixels on the right hand side of the array.
Line Timing: CLAMP and CAL
CLAMP & CAL Line Timing
(SDI address = 0011, D4 = 1)
The timing needed for Line Calibration Mode is shown in
Figure 12. The timing signal CAL gates the XRD98L59s
auto-calibration logic. CAL is active during the end of
line OB pixels.
Most timing generators (TGs) have signals that define
the start of line and end of line OB pixels on the CCD
array. CAL should always be active on start or the end
of line that defines the greatest number of OB pixels
possible. The more OB pixels that the XRD98L59 can
use for its auto-calibration, the faster it can achieve and
maintain calibration. CAL and CLAMP must never be
active at the same time. CLAMP is used to set the
input DC bias voltage. (See Figure 5).

XRD98L59AIG

Mfr. #:
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
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