XRD98L59AIG Datasheet XRD98L59AIGTR-F, XRD98L59AIG-F, XRD98L59AIG | P22-P24

XRD98L59

Rev. 2.00

The ADC input node can be accesed for test purposes

using the ADCIN mode (SDI address 0100). Use the

following procedure to enable the ADCIN mode:

1) In the Serial interface Clock register, set the

Clamp Opt bit low (D4).

2) In the Serial interface Control register, set the

ADCIN bit high (D2).

3) Clock SBLK & SPIX to generate internal

ADC_CLK signal.

4) Apply ADC input signal to CCDin.

In this test mode the analog signal, Vin, applied to CCDin

pin will be converted by the ADC. The ADC output code

is related to Vin by the following rules:

1) For Vin < VRB, ADC output code = 0,

2) For Vin > VRT, ADC output code = 1023,

3) For VRB < Vin < VRT, ADC output code = 1024

x (Vin - VRB) / (VRT - VRB)

CONTROL & RESET REGISTERS

ADCIN Bit

This bit activates a switch that connects CCDin directly

to the ADC input. In this mode, the PGA output is

disabled. See the ADC section for details.

PD Bit (Power Down)

This bit is used to put the chip in the Power Down mode.

It has the same effect as the PD pin. When the PD bit

is high the chip will go into the power down mode, all

conversions stop. When the PD bit is low the chip is in

its normal active mode. In the Power Down mode the

digital output pins are forced to the high impedance mode

and the ADC reference is disconnected. The serial

interface pins remain active in the Power Down mode.

OE Bit (Output Enable)

The ADC digital output bus is equipped with a high

impedance capability. When the OE bit is high the digital

outputs are enabled (active). When the OE bit is low the

digital outputs are in the high impedance mode (not

active). The OE bit only controls the digital output

drivers, all other circuits on the chip will remain active.

RESET Bit

This bit is used to reset all internal registers to default

values. This includes all the serial interface registers as

well as the registers in the calibration logic. To reset the

chip write a “1” to the reset bit. The reset bit will clear itself

after an internal delay, so there is no need to write a “0”

to the reset bit. The chip also has a Power-On-Reset

function (POR) so it will always power up with default

values in all registers. It is recommended that the

XRD98L59 be reset after power is cycled to avoid loading

potentially incorrect serial port data from other ASICs in

the system.

Rev. 2.00

XRD98L59

BLACK LEVEL OFFSET CALIBRATION

CDS 10-bit ADC

Hot Pixel

Clipper

Pixel

Averager

Coarse

Accumulator

Fine

Accumulator

Offset Calibration Logic

2/)

Reg

2/)

CalHold, SpeedUp

Target Offset Code

Gain Code

DB[9:0]

4-bit 10-bit

Black Level

Offset Calibration

Loop

DNS

ManDAC

CDAC, FDAC

From Serial

Interface

Registers

CCD

Signal

CDAC FDAC

DNS

Filter

Figure 15. Black Level Offset Calibration Block Diagram

To get the maximum color resolution and dynamic range,

the XRD98L59 uses a digitally controlled feedback cir-

cuit to correct for offset in the CCD signal as well as offset

in the CDS, PGA & ADC signal path. This calibration is

done while the CCD outputs Optical Black (OB) pixels.

The CAL input signal is used to define when the CCD

output contains OB pixels. The calibration logic will take

into account the internal pipeline delay.

XRD98L59

Rev. 2.00

Hot Pixel Clipper

CCD’s occasionally have hot pixels. These are defective

pixels which always output a bright level. To ensure the

Black Level is not significantly affected by hot pixels in

the OB area, the Hot Pixel Clipper limits pixel data from

the ADC to a maximum value of 127 (7Fh). The Hot Pixel

Clipper is only active when CAL is active. This clipping

only affects the data used by the internal calibration

logic. Data on the digital output bus DB[9:0] is not

clipped.

Pixel Averager

After the clipper, the logic takes the average of the

Optical Black pixels defined by CAL. This averaging

function filters noise.

Offset Difference Using the Target Offset Register

The Target Offset register (Address 0001) value (6 lsb’s)

is subtracted from the OB pixel average. If the difference

is positive, the offset DACs are decremented to reduce

the effective ADC output code. If the difference is

negative, the offset DACs are adjusted to increase the

effective ADC output code. The amount of adjustment is

shown in Figure 16.

Set the Target Offset Register value equal to the desired

black level output code. For example: Set Target Offset

output as 32. Default is code 32 decimal.

Coarse & Fine Accumulators

The Coarse and Fine Accumulators are the registers

which hold the digital codes for the Coarse and Fine

Offset DACs. The Offset DAC adjustments are made by

adding or subtracting to the value in the Fine Accumula-

tor. If there is an overflow or underflow in the Fine

Accumulator, the Fine Accumulator is reset to it’s mid-

scale value, and the Coarse Accumulator is incremented

or decremented accordingly.

CALIBRATION OPTIONS

Speed Up Mode

The purpose of this option is to reduce the amount of time

required for initial convergence of the calibration feed-

back system. The feedback system is designed to have

a slow response time to avoid introducing image arti-

facts. The slow response time is achieved by limiting the

Fine accumulator changes to ± 1 count at a time. The

Speed Up option maintains this slow response while the

difference between the averaged ADC data and the

Target Offset Code is small. But when the difference is

larger than ± 32 lsb’s the Fine accumulator takes large

steps. The actual step size depends on the Gain code,

and is set such that the step will cause no more than a

32 LSB change in the ADC output.

To activate the Speed Up mode write a 1 to the SpeedUp

bit in the Calibration register (bit D3 of Serial Interface

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 64 128 192 256

PGA Code

ADC LSB

= 3.0V

Figure 16. XRD98L59 Offset DAC Step Size in

ADC Output LSBs

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

XRD98L59AIG

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Analog to Digital Converters - ADC

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XRD98L59AIG

XRD98L59AIG

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