25
Rev. 2.00
XRD98L59
Digital Noise Supression (DNS Filter)
To activate the DNS mode, a "1" is written to DNS1 bit in
the Calibration register (bit D2 of Serial Interface Register
#5). By default the DNS mode is active.
In DNS mode, the user has the option to select narrow
band or wide band Noise Suppression Filters by setting
DNS0 bit to a "1" (narrow) or "0" (wide) respectively. Best
performance is achieved by setting DNS1 = "1" and
DNS0 = "0".
Hold Mode
The purpose of this mode is to prevent any changes in the
Fine or Coarse accumulators. The idea is to first run the
calibration normaly so the Fine and Coarse accumulators
converge on the programmed Target Offset Code. Then,
just before acquiring the final image data, activate the
Hold mode. This will ensure the black level offset of the
CDS/PGA does not change while the final image is being
transferred out of the CCD. Once the image has been
acquired from the CCD, turn off the Hold mode so the chip
can continue to compensate for any changes in offset
due to temperature drift or other effects.
To activate the Hold mode write a 1 to the CAL Hold bit
in the Calibration register (bit D4 of Serial Interface
Register #5). By default the Hold mode is not active.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. In the Manual mode, the Coarse
accumulator is programmed by writing to the CDAC
register, the Fine accumulator is programmed by writing
to the FDAC register. The Fine accumulator is a 10 bit
register, but the Serial interface registers are only 8 bits
wide. As shown in the Serial Interface Register Address
Map, two serial interface registers are concatenated to
provide 10 bits to the Fine accumulator.
To activate the Manual mode write a 1 to the ManDAC bit
in the Calibration register (bit D0 of Serial Interface
Register #5). By default the Manual mode is not active.
XRD98L59
26
Rev. 2.00
AV
DD
4-6 3
3
Timing
Generator
V
Driver
CCD
5-10
0.01
µ
F
0.01µF
0.1µF
0.1µF
12V
CLOB
CLDM
SHD
SHP
Serial Ports
ASIC/DSP
10-Bit Digital
Video Input
XRD98L59
SPIX
CAL
CLAMP
12
11
10
9
8
7
4
6
5
15
16
18
19
20
21
22
23
24
14
25
28
CCDin
REFin
AGND
VRB
DB7
DB8
DB9
OV
DD
DB6
DB5
DV
DD
VRT
SCLK
LOAD
SDI
PD
DGND
AV
DD
SBLK
DB1
DB0
DB2
DB3
DB4
OGND
27
26
17
13
1
2
3
AV
DD
AV
DD
Figure 17. Application Diagram; ASIC with External Timing Generator
27
Rev. 2.00
XRD98L59
AV
DD
AV
DD
4-6 3
V
Driver
CCD
5-10
0.01µF
0.01µF
0.1µF
0.1µF
12V
Serial Port
ASIC/DSP
10-Bit Digital
Video Input
XRD98L59
SPIX
CAL
CLAMP
1
12
11
10
9
8
7
4
6
5
15
16
18
19
20
21
22
23
24
14
25
28
CCDin
REFin
AGND
VRB
DB7
DB8
DB9
OVDD
DB6
DB5
DVDD
VRT
SCLK
LOAD
SDI
PD
DGND
AVDD
SBLK
DB1
DB0
DB2
DB3
DB4
OGND
27
26
17
13
Intenal Timing
Generator
3
2
AV
DD
Figure 18. Application Diagram; ASIC with Internal Timing Generator

XRD98L59AIG

Mfr. #:
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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