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932S421BGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
ICS932S421B
IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10
PCIe Gen2 and QPI Clock for Intel-Based Servers
1
DATASHEET
Pin Configuration
Recommended Application:
PCIe Gen 2 & QPI compliant CK410B+ clock for Intel-based
servers
Output Features:
• 4 - 0.7V current-mode differential CPU pairs
• 5 - 0.7V current-mode differential SRC pair
• 4 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - 48MHz
• 2 - REF, 14.318MHz
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
• CPU clocks independent of SRC/PCI clocks
• D2/D3 SMBus address
Key Specifications:
• PCIe Gen 2 compliant SRC outputs
• QPI & FBD 2 compliant CPU clocks
• CPU cycle-cycle jitter: < 50ps
• SRC cycle-cycle jitter: < 125ps
• PCI cycle-cycle jitter: < 500ps
• CPU output skew: < 50ps
• SRC output skew: < 250ps
• ± 100ppm frequency accuracy on all outputs
Functionality
FS_C
1
FS_B
1
FS_A
2
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0 0 0 266.67
0 0 1 133.33
0 1 0 200.00
0 1 1 166.67
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
11 1
1. FS_B and FS_C are three-level inputs. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_A is a low-threshold input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Reserved
100.00 33.33 14.32 48.00
56-pin SSOP & TSSOP
VDDPCI 1 56 FS_C/TEST_SEL
GNDPCI 2 55 REF0
PCICLK0 3 54 REF1
PCICLK1 4 53 VDDREF
PCICLK2 5 52 X1
PCICLK3 6 51 X2
GNDPCI 7 50 GNDREF
VDDPCI 8 49 FS_B/TEST_MODE
PCICLK_F0 9 48 FS_A
PCICLK_F1 10 47 VDDCPU
PCICLK_F2 11 46 CPUCLKT0
VDD48 12 45 CPUCLKC0
48MHz 13 44 VDDCPU
GND48 14 43 CPUCLKT1
VDDSRC 15 42 CPUCLKC1
SRCCLKT0 16 41 GNDCPU
SRCCLKC0 17 40 CPUCLKT2
SRCCLKC1 18 39 CPUCLKC2
SRCCLKT1 19 38 VDDCPU
GNDSRC 20 37 CPUCLKT3
SRCCLKT2 21 36 CPUCLKC3
SRCCLKC2 22 35 VDDA
SRCCLKC3 23 34 GNDA
SRCCLKT3 24 33 IREF
VDDSRC 25 32 NC
SRCCLKT4 26 31 Vtt_PwrGd#/PD
SRCCLKC4 27 30 SDATA
VDDSRC 28 29 SCLK
ICS932S421
IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10
ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
2
Pin Description
Pin # PIN NAME PIN TYPE DESCRIPTION
1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
2 GNDPCI PWR Ground pin for the PCI outputs
3 PCICLK0 OUT PCI clock output.
4 PCICLK1 OUT PCI clock output.
5 PCICLK2 OUT PCI clock output.
6 PCICLK3 OUT PCI clock output.
7 GNDPCI PWR Ground pin for the PCI outputs
8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
9 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# .
10 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# .
11 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# .
12 VDD48 PWR Power pin for the 48MHz output.3.3V
13 48MHz OUT 48MHz clock output.
14 GND48 PWR Ground pin for the 48MHz outputs
15 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
16 SRCCLKT0 OUT True clock of differential SRC clock pair.
17 SRCCLKC0 OUT Complement clock of differential SRC clock pair.
18 SRCCLKC1 OUT Complement clock of differential push-pull SRC clock pair.
19 SRCCLKT1 OUT True clock of differential SRC clock pair.
20 GNDSRC PWR Ground pin for the SRC outputs
21 SRCCLKT2 OUT True clock of differential SRC clock pair.
22 SRCCLKC2 OUT Complement clock of differential SRC clock pair.
23 SRCCLKC3 OUT Complement clock of differential SRC clock pair.
24 SRCCLKT3 OUT True clock of differential SRC clock pair.
25 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
26 SRCCLKT4 OUT True clock of differential SRC clock pair.
27 SRCCLKC4 OUT Complement clock of differential SRC clock pair.
28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10
ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
3
Pin Description (continued)
Pin # PIN NAME T
yp
e Pin Descri
p
tion
29 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
30 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
31 Vtt_PwrGd#/PD IN
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
32 NC N/A No Connection.
33 IREF OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
34 GNDA PWR Ground pin for the PLL core.
35 VDDA PWR 3.3V power for the PLL core.
36 CPUCLKC3 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
37 CPUCLKT3 OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
38 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
39 CPUCLKC2 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
40 CPUCLKT2 OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
41 GNDCPU PWR Ground pin for the CPU outputs
42 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
43 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
44 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
45 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
46 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
47 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
48 FS_A IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
49 FS_B/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input
to select between Hi-Z and REF/N divider mode while in test mode. Refer to
Test Clarification Table.
50 GNDREF PWR Ground pin for the REF outputs.
51 X2 OUT Crystal output, Nominally 14.318MHz
52 X1 IN Crystal input, Nominally 14.318MHz.
53 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
54 REF1 OUT 14.318 MHz reference clock.
55 REF0 OUT 14.318 MHz reference clock.
56 FS_C/TEST_SEL IN
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

932S421BGLFT

Mfr. #:
Buy 932S421BGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK410B+ SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
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