IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10
ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
19
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
PD, Power Down
DPUPC#UPCCRS#CRSICP/FICPBSUFERetoN
0lamroNlamroNlamroNlamroNzHM33zHM84zHM813.411
1ro2*ferI
taolF
taolF2*ferI
taolFro
taolFwoLwo
LwoL1
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Bytes 4 and 5 for additional information.
PD Assertion
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
REF Drive Strength Functionality
Byte6,
bit 4
Byte
10, bit 1
Byte 10,
bit 0 REF1 REF0
0XX1x1x
10 0 1x1x
10 1 1x2x
11 0 2x1x
11 1 2x2x
CPU, SRC and PCI Divider Ratios
Div(3:0) Divider
00000 2
10001 3
20010 5
30011 15
40100 4
50101 6
60110 10
70111 30
81000 8
91001 12
10 1010 20
11 1011 60
12 1100 16
13 1101 24
14 1110 40
15 1111 120
