IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10
ICS932S421B
PCIe Gen2 and QPI Clock for Intel-Based Servers
17
SMBus Table: SRC/PCI Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC N Div8 N Divider Prog bit 8 RW X
Bit 6
SRC N Div9 N Divider Prog bit 9 RW X
Bit 5
SRC M Div5 RW X
Bit 4
SRC M Div4 RW X
Bit 3
SRC M Div3 RW X
Bit 2
SRC M Div2 RW X
Bit 1
SRC M Div1 RW X
Bit 0
SRC M Div0 RW X
SMBus Table: SRC/PCI Frequency Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC N Div7 RW X
Bit 6
SRC N Div6 RW X
Bit 5
SRC N Div5 RW X
Bit 4
SRC N Div4 RW X
Bit 3
SRC N Div3 RW X
Bit 2
SRC N Div2 RW X
Bit 1
SRC N Div1 RW X
Bit 0
SRC N Div0 RW X
SMBus Table: SRC/PCI Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
SRC SSP7 RW X
Bit 6
SRC SSP6 RW X
Bit 5
SRC SSP5 RW X
Bit 4
SRC SSP4 RW X
Bit 3
SRC SSP3 RW X
Bit 2
SRC SSP2 RW X
Bit 1
SRC SSP1 RW X
Bit 0
SRC SSP0 RW X
SMBus Table: SRC/PCI Spread Spectrum Control Register
Pin # Name Control Function Type 0 1 PWD
Bit 7
Reserved Reserved R - - 0
Bit 6
SRC SSP14 RW X
Bit 5
SRC SSP13 RW X
Bit 4
SRC SSP12 RW X
Bit 3
SRC SSP11 RW X
Bit 2
SRC SSP10 RW X
Bit 1
SRC SSP9 RW X
Bit 0
SRC SSP8 RW X
-
-
-
-
-
-
-
Byte 15
-
Byte 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Byte 17
-
-
Spread Spectrum
Programming b(14:8)
These Spread Spectrum bits in
Byte 17 and 18 will program the
spread pecentage of SRC
-
-
-
-
-
-
These Spread Spectrum bits in
Byte 17 and 18 will program the
spread pecentage of SRC
Spread Spectrum
Programming b(7:0)
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power up
= latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
M Divider Programming
bits
N Divider Programming
b(7:0)
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power up
= latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
Byte 18
