NCV7240, NCV7240A, NCV7240B
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DETAILED OPERATING DESCRIPTION
Power Outputs
The NCV7240 provides eight independent 600mA power
transistors with their source connection referenced to the
ground pin and with their drain connection brought out to
individual pins resulting in 8 independent low−side drivers.
Output driver location on one side of the IC layout provides
for optimum pcb layout to the loads.
Internal clamping structures are provided to limit
transient voltages when switching inductive loads. Each
output has an over load detection current of 0.6 A (min)
where the drivers turn−off and stay latched off. An Over
Load Current Shut−Down Delay Time of 3 ms (min) is
designed into the IC as a filter allowing for spikes in current
which may occur during normal operation and allowing for
protection from overload conditions.
Faults can be cleared with the SPI input register
(command 00) or via a power−on−reset. Fault detection is
provided in real time. Detection is provided both during
output turn−on and with output already on. (See Page 17,
Clearing the Fault Registers)
The NCV7240 is available in a SSOP−24 package.
Output Control (SPI)
Each output driver is controlled via a digital SPI port after
the device has powered up (out of POR) and enabled via the
EN pin. The NCV7240 device will go through a power up
reset each time the EN pin is toggled high resulting in a
device setup of default values as described in the Register
Specifics section. Standby Mode, Input Mode, ON Mode,
and OFF Mode are all selectable via the SPI for each channel
independently.
Power up, Power−On Reset (UVLO mode)
Both VDD and VDDA supply an independent
power−on−reset function to the IC. Coming out of
power−on−reset all input bits are set to a 1 (OFF Mode) and
all output bits are set to a 0 except for the TER bit which is
set to a 1. The device cannot operate without both supplies
above their respective power−on reset thresholds with the
exception of LHI mode. During LHI mode, VDD POR is
ignored and the device is only affected by VDDA POR.
The NCV7240 powers up into the Global OFF Mode
without the open circuit diagnostic current enabled. This
allows the device to be turned on via EN = 0 to EN = 1 with
LED loads avoiding illumination of the LED loads
(reference Figure 21 State Diagram). All other paths to
Global OFF Mode enable open circuit diagnostic current.
Table 1. MODES OF OPERATION
Modes of
Operation
Conditions Description
UVLO Mode VDD or VDDA below their respective POR
thresholds
All outputs off in this mode.
Coming out of this mode
with EN = 1 sets all channels in the OFF mode
without open circuit diagnostic current enabled.
With LHI = 1 and EN = x, the part enters limp home mode.
OFF Mode SPI Control
(Command 11)
Output off.
Open circuit diagnostic current is disabled (powerup mode).
Open circuit diagnostic current is enabled (normal mode).
Global OFF Mode SPI Control
All Channels (Command 11)
Output off.
Open circuit diagnostic current is disabled (powerup mode).
Open circuit diagnostic current is enabled (normal mode).
ON Mode SPI Control
(Command 10)
Output on.
Limp Home Mode
(LHI)
LHI = high, EN = x Dedicated output turn on control of
OUT1−OUT4 using IN1−IN4.
OUT5−OUT8 are in OFF Mode.
Low Iq Mode EN = LHI = low Provides a state with the lowest quiescent current for V
DD
and VDDA.
Standby Mode SPI Control
(Command 00)
Provides an OFF state with
Open circuit diagnostic current disabled.
Global
Standby Mode
SPI Control
All Channels (Command 00)
Provides a reduced quiescent current mode.
Provides an OFF state with
Open circuit diagnostic current disabled.
Input Mode SPI Control
(Command 01)
Directs output channel to be driven from INx input pins.
