NCV7240, NCV7240A, NCV7240B
www.onsemi.com
15
Limp Home and PWM operation (INx control)
Pulse Width Modulation techniques are allowed utilizing the parallel inputs (INx).
Output pins (OUTx) are programmed for use in conjunction with the INx pins using the SPI command (command 01).
The LHI pin controls the operation of the INx pins.
LHI = Low and EN = High
With LHI=low, default pairs of outputs are controlled by the INx pins (via SPI programming).
IN1 controls channels OUT1 and OUT5.
IN2 controls channels OUT2 and OUT6.
IN3 controls channels OUT3 and OUT7.
IN4 controls channels OUT4 and OUT8.
Alternatively, any of the eight channels can be commanded off (e.g. if OUT5 is commanded off via a SPI
command, only OUT1 will be controlled via IN1).
Output pins (OUTx) are programmed for use in conjunction with the INx pins
using the SPI command (command 01).
It is important to note faults occurring during PWM operation (LHI = low) must be cleared via the SPI port.
LHI = High
To go into limp home mode, bring LHI=high, the corresponding outputs of IN1−IN4 will turn on or off, and
OUT5−OUT8 will be forced off.
During Limp Home Mode, over load and over temperature sensing are functional, and are reported via the SPI
port. But, since input SPI commands are ignored with LHI = high, driver turn−off (overload or over
temperature) occurring when LHI=high can only be re−initiated by toggling LHI or through a POR of VDDA.
All registers are reset coming out of LHI mode. The device enters OFF mode (EN = 1) or Low Iq Mode (EN
= 0) depending on the state of the EN pin. Open Load diagnostics are disabled in both cases.
UVLO (Under Voltage Lockout with LHI = High)
A breach of VDDA Power−On Reset thresholds will cause the outputs to turn off and enter the UVLO mode. In LHI mode
(LHI = 1), VDD POR is ignored. If VDD is below the operation of SO drive capability, fault information is preserved and can
be retrieved when SO drive capability is restored.
TER
A transmission error bit (TER) is set (”1”) when exiting the Limp Home Mode into Global Off Mode.
See Frame Detection Transmission Error Section for operation details.
Enable Input (EN)
The EN input pin is a logic controlled input with a voltage threshold between 0.8 V and 2.0 V. The device powers up when
EN goes from low to high, and exits Low Iq Mode (with LHI = 0 V) into global Off Mode. Device power up is also controlled
via the Limp Home Input (LHI) as an OR’d condition. The EN input is a don’t care when the LHI pin is driven from low to
high. In this situation, the device enters Limp Home Mode.
Output Drive Clamping
Internal zener diodes (Z1 & Z2, Figure 22) help to protect the output drive transistors from the expected fly back energy
generated from an inductive load turning off. Z1 provides the voltage setting of the clamp (along with V
gs
of the output
transistor and Z2) while Z2 isolates Z1 from normal turn−on activity.
The output clamp voltage is specified between 36 V and 44 V. This includes clamping operation during unpowered input
supplies (VDD and VDDA). Device protection will be provided when the load is driven from an alternative driver source. This
is an important feature when considering protecting for load dump with an un−powered IC.
