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NCV7240ADPR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV7240, NCV7240A, NCV7240B
www.onsemi.com
4
PACKAGE PIN DESCRIPTION
SSOP−24 Symbol Description
1 GND Ground.
2 GND Ground.
3 OUT1 Channel 1 low−side drive output. Requires an external pull−up device for operation.
4 OUT2 Channel 2 low−side drive output. Requires an external pull−up device for operation.
5 OUT3 Channel 3 low−side drive output. Requires an external pull−up device for operation.
6 OUT4 Channel 4 low−side drive output. Requires an external pull−up device for operation.
7 OUT5 Channel 5 low−side drive output. Requires an external pull−up device for operation.
8 OUT6 Channel 6 low−side drive output. Requires an external pull−up device for operation.
9 OUT7 Channel 7 low−side drive output. Requires an external pull−up device for operation.
10 OUT8 Channel 8 low−side drive output. Requires an external pull−up device for operation.
11 GND Ground.
12 GND Ground.
13 VDD Digital Power Supply for SO output (3.3 V or 5 V).
14 IN4 Parallel control of OUT4 and OUT8
Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down will hold the input low.
(120 kW pull down resistor).
15 IN3 Parallel control of OUT3 and OUT7
Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down will hold the input low.
(120 kW pull down resistor).
16 IN2 Parallel control of OUT2 and OUT6.
Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down will hold the input low.
(120 kW pull down resistor).
17 IN1 Parallel control of OUT1 and OUT5.
Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down will hold the input low.
(120 kW pull down resistor).
18 LHI Limp Home Input. Active High.
A high on this pin powers up the device and activates the respective output drive INx designator while
disabling outputs OUT5−OUT8.
Input SPI commands are ignored, but the output register reports faults.
(Read capability only. No write capability.)
All registers are reset coming out of LHI mode.
Ground if not used for best EMI performance.
Alternatively keep open and internal pull−down resistor (120 kW) will hold the input low.
19 SO SPI serial data output. Output high voltage level referenced to pin VDD.
20 SCLK
SPI clock (120 kW pull down resistor).
21 EN
Global Enable (active high). (120 kW pull down resistor).
22 SI
SPI serial data input (120 kW pull down resistor).
23 CSB
SPI Chip Select ”Bar” (120 kW pull up resistor to VDD).
24 VDDA Analog Power Supply Input voltage (5 V).
NCV7240, NCV7240A, NCV7240B
www.onsemi.com
5
MAXIMUM RATINGS
Parameter Min Max Unit
Supply Input Voltage (VDDA, VDD)
DC
−0.3 5.5
V
Digital I/O pin voltage
(EN, LHI, Inx, CSB, SCLK, SI)
(SO)
−0.3
−0.3
5.5
V
DD
+ 0.3
V
High Voltage Pins (OUTx)
DC
Peak Transient
−0.3 36
44 (Note 1)
V
Output Current (OUTx) −1 1.3 A
Clamping Energy
Maximum (single pulse)
Repetitive (multiple pulse) (Note 2)
−
−
75
−
mJ
Operating Junction Temperature Range −40 150 °C
Storage Temperature Range −55 150 °C
ESD Capability,
Human body model (100 pF, 1.5 kW) (OUTx pins)
Human body model (100 pF, 1.5 kW) (all other pins)
−4000
−2000
4000
2000
V
ESD Capability
Machine Model (200 pF)
−200 200
V
AECQ10x−12−RevA
Short Circuit Reliability Characterization
Grade A −
PACKAGE
Moisture Sensitivity Level
MSL2 −
Lead Temperature Soldering: SMD style only, Reflow (Note 3)
Pb−Free Part 60 − 150 sec above 217°C, 40 sec max at peak
265 peak °C
Package Thermal Resistance (per JESD51)
SSOP−24
Junction−to−Ambient (1s0p + 600 mm
2
Cu) (Note 4)
Junction−to−Ambient (2s2p) (Notes 4 and 5)
Junction−to−Pin (pins 1, 2, 11, 12) (Note 6)
68
62
30
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Internally limited. Specification applies to unpowered and powered modes. (0 V to VDDA, 0 V to VDD)
2. Testing particulars, 2M pulses, V
bat
= 15 V, 63 W, 390 mH, T
A
= 25°C. (See Figure 4)
3. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
and Application Note AND8083/D.
4. 76 mm x 76 mm x 1.5 mm FR4 PCB with additional heat spreading copper (2 oz) of 600 mm
2
, LS1 to LS8 dissipating 100 mW each. No
vias.
5. Include 2 inner 1 oz copper layers. No vias.
6. One output dissipating 100 mW.
Figure 4. Repetitive Clamping Energy Test
NCV7240, NCV7240A, NCV7240B
www.onsemi.com
6
ELECTRICAL CHARACTERISTICS (3.0 V < VDD < VDDA, 4.5 V < VDDA (Note 7) < 5.5 V, −40°C v T
J
v 150°C, EN = VDD,
LHI = 0 V unless otherwise specified).
Characteristic
Conditions Min Typ Max Unit
GENERAL
Operating Current (VDDA)
ON Mode
(All Channels On)
− 3 5
mA
Quiescent Current (VDDA)
Global Standby Mode
(All Channels Off)
SI = SCLK = 0 V, CSB = VDD
T
J
= 25°C
T
J
= 85°C
T
J
= 150°C
−
−
−
32
35
40
mA
Quiescent Current (VDDA)
Low Iq Mode
SI = SCLK = EN = 0 V, CSB = VDD
T
J
= 25°C
T
J
= 85°C
T
J
= 150°C
−
−
−
−
−
−
10
10
20
mA
Operating Current (VDD)
ON Mode
(All Channels On)
EN=high, SCLK = Inx = 0 V,
CSB = VDD = VDDA − 0.3 0.5
mA
Quiescent Current (VDD)
Global Standby Mode
(All Channels Off)
CSB = VDD = VDDA, f
SCLK
= 0 Hz
T
J
= 25°C
T
J
= 85°C
T
J
= 150°C
−
−
−
−
−
−
20
20
40
mA
Quiescent Current (VDD)
Low Iq Mode
EN = 0 V
T
J
= 25°C
T
J
= 85°C
T
J
= 150°C
−
−
−
−
−
−
5
5
20
mA
Power−on Reset threshold (VDDA) VDDA rising − 3.80 4.15 V
Power−on Reset Hysteresis (VDDA) 150 200 350 mV
Power−on Reset threshold (VDD) VDD rising − 2.4 2.7 V
Power−on Reset Hysteresis (VDD) 75 100 240 mV
Thermal Shutdown (Note 8) Not ATE tested. 150 175 200 °C
Thermal Hysteresis Not ATE tested. 10 25 − °C
OUTPUT DRIVER
Output Transistor R
DS(on)
IOUTx = 180 mA − 1.5 3.0
W
Overload Detection Current 0.6 0.95 1.3 A
Output Leakage OUTx = 13.5 V, 25°C
OUTx = 13.5 V
OUTx = 35 V
−
−
−
−
−
−
1
5
10
mA
Output Clamp Voltage VDD = 0 V to 5.5 V
VDDA = 0 V to 5.5 V
IOUTx = 50 mA
36 40 44 V
Output Body Diode Voltage IOUTx = −180mA − − 1.5 V
Open Load Detection Threshold Voltage
(Vol)
1.0 1.75 2.5 V
Open Load Diagnostic Sink Current
(Iol)
1 V < OUTx < 13.5 V, Output Disabled 20 60 100
mA
OUTPUT TIMING SPECIFICATIONS
Enable (EN) wake−up time
CSB = 0 V
EN going high 80% to SO active
− − 200
ms
Enable (EN) and LHI (Note 9)
Signal Duration
50 − −
ms
7. Reduced performance down to 4 V provided VDDA Power−On Reset threshold has not been breached.
8. Each output driver is protected by its’ own individual thermal sensor.
9. Input signals H→L→H greater than 50usec are guaranteed to be detected.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV7240ADPR2G

Mfr. #:
Buy NCV7240ADPR2G
Manufacturer:
ON Semiconductor
Description:
Gate Drivers 8 CHANNEL LOW SIDE DRIVER
Lifecycle:
New from this manufacturer.
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